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TMP32C6411ZLZ Datasheet(PDF) 102 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 102 Page - Texas Instruments |
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102 / 119 page  TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING timing requirements for McBSP† (see Figure 51) NO. −300 UNIT NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 4P or 6.67‡§¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1# ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 9 ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1.3 ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3 ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 8 ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0.9 ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 3.1 ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 9 ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1.3 ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. § P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. ¶ Use whichever value is greater. # This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle. |
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