TMP32C6411ZLZ datasheet(83/119 Pages) TI

No. de pieza	TMP32C6411ZLZ

Descripción Electrónicos	FIXED POINT DIGITAL SIGNAL PROCESSOR

PDF	119 Pages

Scroll/Zoom	100%

Fabricante Electrónico	TI [Texas Instruments]

Página de inicio	http://www.ti.com

Logo

83 / 119 page

TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

ECLKOUTx

CEx

BE[3:0]

EA[12:3]

ED[31:0]

EA13

AOE/SDRAS/SOE†

ARE/SDCAS/SADS/SRE†

AWE/SDWE/SWE†

EA[22:14]

BE1

BE2

BE3

BE4

Bank

Column

READ

PDT‡

PDTR/W

† ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

‡ PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data

is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data

phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,

respectively. PDTRL equals 00 (zero latency) in Figure 27.

Figure 27. SDRAM Read Command (CAS Latency 3)

TMP32C6411ZLZ Datasheet(PDF) 83 Page - Texas Instruments