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TMP32C6411ZLZ Datasheet(PDF) 19 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 119 page  TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 19 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 5. L2 Cache Registers (Continued) HEX ADDRESS RANGE COMMENTS REGISTER NAME ACRONYM 0184 82D8 MAR182 Controls EMIF CE3 range B600 0000 − B6FF FFFF 0184 82DC MAR183 Controls EMIF CE3 range B700 0000 − B7FF FFFF 0184 82E0 MAR184 Controls EMIF CE3 range B800 0000 − B8FF FFFF 0184 82E4 MAR185 Controls EMIF CE3 range B900 0000 − B9FF FFFF 0184 82E8 MAR186 Controls EMIF CE3 range BA00 0000 − BAFF FFFF 0184 82EC MAR187 Controls EMIF CE3 range BB00 0000 − BBFF FFFF 0184 82F0 MAR188 Controls EMIF CE3 range BC00 0000 − BCFF FFFF 0184 82F4 MAR189 Controls EMIF CE3 range BD00 0000 − BDFF FFFF 0184 82F8 MAR190 Controls EMIF CE3 range BE00 0000 − BEFF FFFF 0184 82FC MAR191 Controls EMIF CE3 range BF00 0000 − BFFF FFFF 0184 8300 −0184 83FC MAR192 to MAR255 Reserved 0184 8400 −0187 FFFF − Reserved Table 6. EDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 FF9C EPRH Event polarity high register 01A0 FFA4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFB0 ERH Event high register 01A0 FFB4 EERH Event enable high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFC0 PQAR0 Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC PQAR3 Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFF0 ERL Event low register 01A0 FFF4 EERL Event enable low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 − 01A3 FFFF – Reserved peripheral register descriptions (continued) |
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