TMP32C6411ZLZ datasheet(99/119 Pages) TI

No. de pieza	TMP32C6411ZLZ

Descripción Electrónicos	FIXED POINT DIGITAL SIGNAL PROCESSOR

PDF	119 Pages

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Fabricante Electrónico	TI [Texas Instruments]

Página de inicio	http://www.ti.com

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99 / 119 page

TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING

timing requirements for PCLK†‡ (see Figure 47)

NO.

−300

UNIT

NO.

MIN

MAX

UNIT

tc(PCLK)

Cycle time, PCLK

30(or 8P§)

tw(PCLKH)

Pulse duration, PCLK high

tw(PCLKL)

Pulse duration, PCLK low

tsr(PCLK)

∆v/∆t slew rate, PCLK

V/ns

† For 3.3 V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.

‡ P = 1/CPU clock frequency in ns. For example when running parts at 300 MHz, use P = 3.33 ns.

§ Select the parameter value of 30 ns or 8P, whichever is greater.

PCLK

0.4 DVDD V MIN

Peak to Peak for

3.3V signaling

Figure 47. PCLK Timing

timing requirements for PCI reset (see Figure 48)

NO.

−300

UNIT

NO.

MIN

MAX

UNIT

tw(PRST)

Pulse duration, PRST

tsu(PCLKA-PRSTH)

Setup time, PCLK active before PRST high

100

µs

PRST

PCLK

Figure 48. PCI Reset (PRST) Timing

TMP32C6411ZLZ Datasheet(PDF) 99 Page - Texas Instruments

TMP32C6411ZLZ Datasheet(HTML) 99 Page - Texas Instruments

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