TMP32C6411ZLZ datasheet(65/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

IEEE 1149.1 JTAG compatibility statement

The TMS320C6411 DSP requires that both TRST and RESET be asserted upon power up to be properly

initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are

required for proper operation.

Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected

after TRST is asserted.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the

DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface

and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG

controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be released in

order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions

work correctly independent of current state of RESET.

For maximum reliability, the TMS320C6411 DSP includes an internal pulldown (IPD) on the TRST pin to ensure

that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly

initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG

controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of

JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST high before

attempting any emulation or boundary scan operations.

Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and

EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode. For

more detailed information, see the terminal functions section of this data sheet.

Note: The DESIGN_WARNING section of the TMS320C6411 BSDL file contains information and constraints

regarding proper device operation while in Boundary Scan Mode.

EMIF device speed

The rated EMIF speed of this device only applies to the SDRAM interface when in a system that meets the

following requirements:

−

1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF

−

up to 1 CE space of buffers connected to EMIF

−

EMIF trace lengths between 1 and 3 inches

−

143-MHz SDRAM for 75-MHz operation

Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.

Verification of AC timings is mandatory when using configurations other than those specified above.

TI recommends utilizing the input/output buffer information specification (IBIS) models to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models

for Timing Analysis application report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see

the Terminal Functions table for the EMIF output signals).

TMP32C6411ZLZ Datasheet(PDF) 65 Page - Texas Instruments

TMP32C6411ZLZ Datasheet(HTML) 65 Page - Texas Instruments

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