TMP32C6411ZLZ datasheet(84/119 Pages) TI

No. de pieza	TMP32C6411ZLZ

Descripción Electrónicos	FIXED POINT DIGITAL SIGNAL PROCESSOR

PDF	119 Pages

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Fabricante Electrónico	TI [Texas Instruments]

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

ECLKOUTx

CEx

BE[3:0]

EA[12:3]

ED[31:0]

AOE/SDRAS/SOE†

ARE/SDCAS/SADS/SRE†

AWE/SDWE/SWE†

EA13

EA[22:14]

BE1

BE2

BE3

BE4

Bank

Column

WRITE

PDT‡

PDTR/W

† ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

‡ PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data

is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data

phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,

01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.

Figure 28. SDRAM Write Command

TMP32C6411ZLZ Datasheet(PDF) 84 Page - Texas Instruments