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TMP32C6411ZLZ Datasheet(PDF) 78 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 119 page ![]() TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING timing requirements for programmable synchronous interface cycles (see Figure 24) NO. −300 UNIT NO. MIN MAX UNIT 6 tsu(EDV-EKOxH) Setup time, read EDx valid before ECLKOUTx high 6.4 ns 7 th(EKOxH-EDV) Hold time, read EDx valid after ECLKOUTx high 1.5 ns switching characteristics over recommended operating conditions for programmable synchronous interface cycles† (see Figure 24−Figure 26) NO. PARAMETER −300 UNIT NO. PARAMETER MIN MAX UNIT 1 td(EKOxH-CEV) Delay time, ECLKOUTx high to CEx valid 1.3 9.7 ns 2 td(EKOxH-BEV) Delay time, ECLKOUTx high to BEx valid 9.7 ns 3 td(EKOxH-BEIV) Delay time, ECLKOUTx high to BEx invalid 1.3 ns 4 td(EKOxH-EAV) Delay time, ECLKOUTx high to EAx valid 9.7 ns 5 td(EKOxH-EAIV) Delay time, ECLKOUTx high to EAx invalid 1.3 ns 8 td(EKOxH-ADSV) Delay time, ECLKOUTx high to SADS/SRE valid 1.3 9.7 ns 9 td(EKOxH-OEV) Delay time, ECLKOUTx high to, SOE valid 1.3 9.7 ns 10 td(EKOxH-EDV) Delay time, ECLKOUTx high to EDx valid 9.7 ns 11 td(EKOxH-EDIV) Delay time, ECLKOUTx high to EDx invalid 1.3 ns 12 td(EKOxH-WEV) Delay time, ECLKOUTx high to SWE valid 1.3 9.7 ns † The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 |
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