TMP32C6411ZLZ datasheet(106/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

106

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)

timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 53)

−300

NO.

MASTER

SLAVE

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

2 − 12P

th(CKXL-DRV)

Hold time, DR valid after CLKX low

5 + 24P

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics over recommended operating conditions for McBSP as SPI Master or

Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 53)

−300

NO.

PARAMETER

MASTER§

SLAVE

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(CKXL-FXL)

Hold time, FSX low after CLKX low¶

T − 2

T + 3

td(FXL-CKXH)

Delay time, FSX low to CLKX high#

L − 2

L + 3

td(CKXH-DXV)

Delay time, CLKX high to DX valid

−2

12P+2.8

20P+17

tdis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit from

CLKX low

L − 2

L + 3

tdis(FXH-DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

4P+3

12P+17

td(FXL-DXV)

Delay time, FSX low to DX valid

8P+1.8

16P+17

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

§ S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =

CLKX period = (1 + CLKGDV) * S

H =

CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

# FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock

(CLKX).

TMP32C6411ZLZ Datasheet(PDF) 106 Page - Texas Instruments

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