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TMP32C6411ZLZ Datasheet(PDF) 61 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 119 page  TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 power-down mode logic Figure 9 shows the power-down mode logic on the C6411. PWRD Internal Clock Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET CLKOUT6 PD3 Internal Peripherals CLKOUT4 Clock and Dividers Distribution † External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. TMS320C6411 Figure 9. Power-Down Mode Logic† triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10 and described in Table 25. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). |
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