TMP32C6411ZLZ datasheet(69/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

(see note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from

the data sheet timings.

3.5 nH

Device Pin

(see note)

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 12. Test Load Circuit for AC Timing Measurements

The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate

the maximum load the device is capable of driving.

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

Vref = 1.5 V

Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX

and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for

PCI output clocks.

Vref = VIL MAX (or VOL MAX or

Vref = VIH MIN (or VOH MIN or

VIHP MIN or VOHP MIN)

VILP MAX or VOLP MAX)

Figure 14. Rise and Fall Transition Time Voltage Reference Levels

signal transition rates

All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).

TMP32C6411ZLZ Datasheet(PDF) 69 Page - Texas Instruments