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TMP32C6411ZLZ Datasheet(PDF) 15 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 119 page ![]() TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 L2 architecture expanded Figure 2 shows the detail of the L2 architecture on the TMS320C6411 device. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610). 0x0000 0000 011 010 001 111 0x0002 0000 000 L2MODE L2 Memory Block Base Address 0x0003 8000 0x0003 0000 128K-Byte SRAM 64K-Byte RAM 32K-Byte RAM 0x0003 FFFF 32K-Byte RAM Figure 2. TMS320C6411 L2 Architecture Memory Configuration |
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