TMP32C6411ZLZ datasheet(89/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

HOLD/HOLDA TIMING

timing requirements for the HOLD/HOLDA cycles† (see Figure 35)

NO.

−300

UNIT

NO.

MIN

MAX

UNIT

th(HOLDAL-HOLDL)

Hold time, HOLD low after HOLDA low

† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.

switching characteristics over recommended operating conditions for the HOLD/HOLDA

cycles†‡§ (see Figure 35)

NO.

PARAMETER

−300

UNIT

NO.

PARAMETER

MIN

MAX

UNIT

td(HOLDL-EMHZ)

Delay time, HOLD low to EMIF Bus high impedance

td(EMHZ-HOLDAL)

Delay time, EMIF Bus high impedance to HOLDA low

td(HOLDH-EMLZ)

Delay time, HOLD high to EMIF Bus low impedance

td(EMLZ-HOLDAH)

Delay time, EMIF Bus low impedance to HOLDA high

td(HOLDL-EKOHZ)

Delay time, HOLD low to ECLKOUTx high impedance

td(HOLDH-EKOLZ)

Delay time, HOLD high to ECLKOUTx low impedance

† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.

‡ EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[22:3], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE , SDCKE,

SOE3, and PDT.

§ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,

ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.

¶ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay

time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

HOLD

HOLDA

EMIF Bus†

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

C6411

ECLKOUTx‡

(EKxHZ = 0)

ECLKOUTx‡

(EKxHZ = 1)

† EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[22:3], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE, SDCKE,

SOE3, and PDT.

‡ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,

ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.

Figure 35. HOLD/HOLDA Timing

TMP32C6411ZLZ Datasheet(PDF) 89 Page - Texas Instruments

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