TMP32C6411ZLZ datasheet(63/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PD2 and PD3 modes can only be aborted by device reset. Table 25 summarizes all the power-down modes.

Table 25. Characteristics of the Power-Down Modes

PRWD FIELD

(BITS 15−10)

POWER-DOWN

MODE

WAKE-UP METHOD

EFFECT ON CHIP’S OPERATION

000000

No power-down

—

001001

PD1

Wake by an enabled interrupt

CPU halted (except for the interrupt logic)

Power-down mode blocks the internal clock inputs at the

010001

PD1

Wake by an enabled or

non-enabled interrupt

Power-down mode blocks the internal clock inputs at the

boundary of the CPU, preventing most of the CPU’s logic from

switching. During PD1, EDMA transactions can proceed

between peripherals and internal memory.

011010

PD2†

Wake by a device reset

Output clock from PLL is halted, stopping the internal clock

structure from switching and resulting in the entire chip being

halted. All register and internal RAM contents are preserved. All

functional I/O “freeze” in the last state when the PLL clock is

turned off.

011100

PD3†

Wake by a device reset

Input clock to the PLL stops generating clocks. All register and

internal RAM contents are preserved. All functional I/O “freeze” in

the last state when the PLL clock is turned off. Following reset, the

PLL needs time to re-lock, just as it does following power-up.

Wake-up from PD3 takes longer than wake-up from PD2 because

the PLL needs to be re-locked, just as it does following power-up.

All others

Reserved

—

† When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or

peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,

peripherals will not operate according to specifications.

C64x power-down mode with an emulator

If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow

the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed

from the header. If power measurements are to be performed when in a power-down mode, the emulator cable

should be removed.

When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution

command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP

reset will be required to get the DSP out of PD2/PD3.

power-supply sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,

systems should be designed to ensure that neither supply is powered up for extended periods of time

(

>1 second) if the other supply is below the proper operating voltage.

power-supply design considerations

A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O

power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11).

TMP32C6411ZLZ Datasheet(PDF) 63 Page - Texas Instruments

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