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TMP32C6411ZLZ Datasheet(PDF) 68 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 119 page ![]() TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT VOH High-level output voltage (except PCI) DVDD = MIN, IOH = MAX 2.4 V VOHP High-level output voltage (PCI) IOHP = −0.5 mA, DVDD = 3.3 V 0.9DVDD¶ V VOL Low-level output voltage (except PCI) DVDD = MIN, IOL = MAX 0.4 V VOLP Low-level output voltage (PCI) IOLP = 1.5 mA, DVDD = 3.3 V 0.1DVDD¶ V VI = VSS to DVDD no opposing internal resistor ±10 uA II Input current (except PCI) VI = VSS to DVDD opposing internal pullup resistor‡ 50 100 150 uA VI = VSS to DVDD opposing internal pulldown resistor‡ −150 −100 −50 uA IIP Input leakage current (PCI)§ 0 < VIP < DVDD,DVDD = 3.3 V ±10 uA EMIF, CLKOUT4, CLKOUT6, EMUx −16 mA IOH High-level output current Timer, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP −8 mA PCI/HPI −0.5§¶ mA EMIF, CLKOUT4, CLKOUT6, EMUx 16 mA IOL Low-level output current Timer, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP 8 mA PCI/HPI 1.5¶ mA IOZ Off-state output current VO = DVDD or 0 V ±10 uA ICDD Core supply current# CVDD = 1.2 V, CPU clock = 300 MHz 550 mA IDDD I/O supply current# DVDD = 3.3 V, CPU clock = 300 MHz 125 mA Ci Input capacitance 10 pF Co Output capacitance 10 pF † For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. ‡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. § PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. ¶ These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4, respectively. # Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6411 Power Consumption Summary application report (literature number SPRA373). recommended clock and control signal transition behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. |
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