TMP32C6411ZLZ datasheet(82/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 27)

NO.

−300

UNIT

NO.

MIN

MAX

UNIT

tsu(EDV-EKO1H)

Setup time, read EDx valid before ECLKOUTx high

5.4

th(EKO1H-EDV)

Hold time, read EDx valid after ECLKOUTx high

2.5

switching characteristics over recommended operating conditions for synchronous DRAM cycles

(see Figure 27−Figure 34)

NO.

PARAMETER

−300

UNIT

NO.

PARAMETER

MIN

MAX

UNIT

td(EKO1H-CEV)

Delay time, ECLKOUTx high to CEx valid

1.3

9.7

td(EKO1H-BEV)

Delay time, ECLKOUTx high to BEx valid

9.7

td(EKO1H-BEIV)

Delay time, ECLKOUTx high to BEx invalid

1.3

td(EKO1H-EAV)

Delay time, ECLKOUTx high to EAx valid

9.7

td(EKO1H-EAIV)

Delay time, ECLKOUTx high to EAx invalid

1.3

td(EKO1H-CASV)

Delay time, ECLKOUTx high to SDCAS valid

1.3

9.7

td(EKO1H-EDV)

Delay time, ECLKOUTx high to EDx valid

9.7

td(EKO1H-EDIV)

Delay time, ECLKOUTx high to EDx invalid

1.3

td(EKO1H-WEV)

Delay time, ECLKOUTx high to SDWE valid

1.3

9.7

td(EKO1H-RAS)

Delay time, ECLKOUTx high to SDRAS valid

1.3

9.7

td(EKO1H-SDCKEV) Delay time, ECLKOUTx high to SDCKE valid

1.3

9.7

td(EKO1H-PDTV)

Delay time, ECLKOUTx high to PDT valid

1.3

9.7

TMP32C6411ZLZ Datasheet(PDF) 82 Page - Texas Instruments

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