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TMP32C6411ZLZ Datasheet(PDF) 36 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 119 page  TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DEVICE CONFIGURATIONS (CONTINUED) Table 22. C6411 Device Multiplexed Pins† MULTIPLEXED PINS DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION NAME NO. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION CLKOUT4/GP1 AE6 CLKOUT4 GP1EN = 0 (disabled) These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be CLKOUT6/GP2 AD6 CLKOUT6 GP2EN = 0 (disabled) GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output GP9/PIDSEL M3 To use GP[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GP10/PCBE3 L2 To use GP[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable GP11/PREQ F1 GPxEN = 0 (disabled) GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GP12/PGNT J3 None GPxEN = 0 (disabled) PCI_EN = 0 (disabled)† Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GP13/PINTA G4 None PCI_EN = 0 (disabled)† GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GP14/PCLK F2 GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GP15/PRST G3 GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output HD[31:0]/AD[31:0] ‡ HD[31:0] HAS/PPAR T3 HAS HCNTL1/PDEVSEL R1 HCNTL1 By default, HPI is enabled upon reset HCNTL0/PSTOP T4 HCNTL0 By default, HPI is enabled upon reset (PCI is disabled). HDS1/PSERR T1 HDS1 PCI_EN = 0 (disabled)† (PCI is disabled). To enable the PCI peripheral an external HDS2/PCBE1 T2 HDS2 PCI_EN = 0 (disabled)† To enable the PCI peripheral an external pullup resistor (1 k Ω) must be provided on the PCI_EN pin (setting PCI_EN = 1 HR/W/PCBE2 P1 HR/W pullup resistor (1 k ) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset and keeping valid “1” after HHWIL/PTRDY R3 HHWIL (HPI16 only) at reset and keeping valid “1” after reset). HINT/PFRAME R4 HINT reset). HCS/PPERR R2 HCS HRDY/PIRDY P4 HRDY CLOCK/PLL CONFIGURATION CLKIN H4 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP1§ AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be pro- grammed as a GPIO 1 pin (I/O/Z). CLKOUT6/GP2§ AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be pro- grammed as a GPIO 2 pin (I/O/Z). † All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0]. ‡ For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table. |
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