TMP32C6411ZLZ datasheet(59/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock PLL (continued)

PLLMULT

PLLCLK

CLKMODE0

CLKIN

EMI

filter

3.3 V

00 01 10

CPU Clock

Configuration Bus

Timer Internal Clock

CLKOUT4,

McBSP Internal Clock

CLKOUT6

ECLKIN_SEL[1:0]

EMIF

00 01 10

EK2RATE

(GBLCTL.[19,18])

ECLKOUT2

ECLKOUT1

PLL x6

µF 0.1 µF

ECLKIN

(For the PLL Options, CLKMODE0 Pin Setup, and

PLL Clock Frequency Ranges, see Table 24.)

Internal to C6411

PLLV

(See Table 24)

NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000

 DSP device as possible. For the best

performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or

components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI

Filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.

Figure 6. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode

Table 24. TMS320C6411 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡

GLZ and ZLZ PACKAGE − 23 x 23 mm BGA

CLKMODE0

CLKMODE

(PLL MULTIPLY

FACTORS)

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

RANGE (MHz)

CLKOUT4

RANGE (MHz)

CLKOUT6

RANGE (MHz)

TYPICAL

LOCK TIME

(

µs)§

Bypass (x1) [default]

30−75.75

7.5−18.93

5−12.62

N/A

30−50.5

180−303

45−75.75

30−50.5

† These clock frequency range values are applicable to a C6411−300 speed device.

‡ Use an external pullup resistor on the CLKMODE0 pin to set the C6411 device to the valid PLL multiply clock mode (x6). With an internal pulldown

resistor on the CLKMODE0 pin, the default clock mode is x1 (bypass).

§ Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if

the typical lock time is specified as 100

µs, the maximum value may be as long as 250 µs.

TMP32C6411ZLZ Datasheet(PDF) 59 Page - Texas Instruments

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