| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TMP32C6411ZLZ Datasheet(PDF) 39 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMP32C6411ZLZ Datasheet(HTML) 39 Page - Texas Instruments |
|
39 / 119 page ![]() TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 39 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE† IPD/ ‡ DESCRIPTION NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED) GP0 AF6 I/O/Z IPD GPIO 0 pin. The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). GP8 AE4 I/O/Z IPD This pin has no function at default [default] or this pin can be programmed as a GPIO 8 pin (I/O/Z). CLKOUT6/GP2§ AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKOUT4/GP1§ AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) HINT/ PFRAME§ R4 I/O/Z Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z) HCNTL1/ PDEVSEL§ R1 I/O/Z Host control − selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z). HCNTL0/ PSTOP§ T4 I/O/Z Host control − selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) HHWIL/PTRDY§ R3 I/O/Z Host half-word select − first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z) HR/W/PCBE2§ P1 I/O/Z Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) HAS/PPAR§ T3 I/O/Z Host address strobe (I) [default] or PCI parity (I/O/Z) HCS/PPERR§ R2 I/O/Z Host chip select (I) [default] or PCI parity error (I/O/Z) HDS1/PSERR§ T1 I/O/Z Host data strobe 1 (I) [default] or PCI system error (I/O/Z) HDS2/PCBE1§ T2 I/O/Z Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) HRDY/PIRDY§ P4 I/O/Z Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z). HD31/AD31§ J2 HD30/AD30§ K3 HD29/AD29§ J1 Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) HD28/AD28§ K4 Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) HD27/AD27§ K2 As HPI data bus (PCI_EN pin = 0) Used for transfer of data, address, and control HD26/AD26§ L3 As HPI data bus (PCI_EN pin = 0) • Used for transfer of data, address, and control • Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor HD25/AD25§ K1 • Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor pullup/pulldown resistor on the HD5 pin: HD24/AD24§ L4 pullup/pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16. HD23/AD23§ L1 I/O/Z HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are HD22/AD22§ M4 I/O/Z (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD21/AD21§ M2 reserved pins in the high-impedance state.) HD5 pin = 1: HPI operates as an HPI32. HD20/AD20§ N4 HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) HD19/AD19§ M1 (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) HD18/AD18§ N5 As PCI data-address bus (PCI_EN pin = 1) Used for transfer of data and address HD17/AD17§ N1 • Used for transfer of data and address HD16/AD16§ P5 HD15/AD15§ U4 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used, unless otherwise noted.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |