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TMP32C6411ZLZ Datasheet(PDF) 40 Page - Texas Instruments

No. de pieza TMP32C6411ZLZ
Descripción Electrónicos  FIXED POINT DIGITAL SIGNAL PROCESSOR
PDF  119 Pages
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TMP32C6411ZLZ Datasheet(HTML) 40 Page - Texas Instruments

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TMS320C6411
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS196H − MARCH 2002 − REVISED JULY 2004
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL
TYPE†
IPD/
‡
DESCRIPTION
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) (CONTINUED)
HD14/AD14§
U1
HD13/AD13§
U3
Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z)
HD12/AD12§
U2
Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z)
HD11/AD11§
V4
As HPI data bus (PCI_EN pin = 0)
Used for transfer of data, address, and control
HD10/AD10§
V1
As HPI data bus (PCI_EN pin = 0)
• Used for transfer of data, address, and control
• Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor
HD9/AD9§
V3
• Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor
pullup/pulldown resistor on the HD5 pin:
HD8/AD8§
V2
pullup/pulldown resistor on the HD5 pin:
HD5 pin = 0: HPI operates as an HPI16.
HD7/AD7§
W2
I/O/Z
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
HD6/AD6§
W4
I/O/Z
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
HD5/AD5§
Y1
reserved pins in the high-impedance state.)
HD5 pin = 1: HPI operates as an HPI32.
HD4/AD4§
Y3
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD3/AD3§
Y2
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
HD2/AD2§
Y4
As PCI data-address bus (PCI_EN pin = 1)
Used for transfer of data and address
HD1/AD1§
AA1
• Used for transfer of data and address
HD0/AD0§
AA3
PCBE0§
W3
I/O/Z
PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
XSP_CS
AD1
O
IPD
PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
XSP_CLK
AC2
I/O/Z
IPD
This pin has no function at default [default] or when PCI is enabled (PCI_EN = 1), this pin is the
PCI serial interface clock (O).
XSP_DI
AB3
I
IPU
This pin has no function at default [default] or when PCI is enabled (PCI_EN = 1), this pin is the
PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the
serial PROM.
XSP_DO
AA2
O/Z
IPU
This pin has no function at default [default] or when PCI is enabled (PCI_EN = 1), this pin is the
PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the
serial PROM.
GP15/PRST§
G3
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GP14/PCLK§
F2
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
GP13/PINTA§
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GP12/PGNT§
J3
I/O/Z
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
GP11/PREQ§
F1
I/O/Z
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GP10/PCBE3§
L2
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GP9/PIDSEL§
M3
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
Ω resistor should be used, unless otherwise noted.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.



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