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TMP32C6411ZLZ Datasheet(PDF) 41 Page - Texas Instruments |
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TMP32C6411ZLZ Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 119 page  TMS320C6411 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS196H − MARCH 2002 − REVISED JULY 2004 41 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL TYPE† IPD/ ‡ DESCRIPTION NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIF (32-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY§ CE3 L26 O/Z IPU EMIF memory space enables CE2 K23 O/Z IPU EMIF memory space enables • Enabled by bits 28 through 31 of the word address CE1 K24 O/Z IPU • Enabled by bits 28 through 31 of the word address • Only one pin is asserted during any external data access CE0 K25 O/Z IPU • Only one pin is asserted during any external data access BE3 M25 O/Z IPU EMIF byte-enable control Decoded from the low-order address bits. The number of address bits or byte enables BE2 M26 O/Z IPU EMIF byte-enable control • Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. BE1 L23 O/Z IPU used depends on the width of external memory. • Byte-write enables for most types of memory BE0 L24 O/Z IPU • Byte-write enables for most types of memory • Can be directly connected to SDRAM read and write mask signal (SDQM) PDT M22 O/Z IPU EMIF peripheral data transfer, allows direct transfer between external peripherals EMIF (32-BIT) − BUS ARBITRATION§ HOLDA N22 O IPU EMIF hold-request-acknowledge to the host HOLD V23 I IPU EMIF hold request from the host BUSREQ P22 O IPU EMIF bus request output EMIF (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL§ ECLKIN H25 I IPD EMIF external input clock. The EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the ECLKIN_SEL[1:0] pins. AECLKIN is the default for the EMIF input clock. ECLKOUT2 J23 O/Z IPD EMIF output clock 2. Programmable to be EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. ECLKOUT1 J26 O/Z IPD EMIF output clock 1 at EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) frequency. ARE/ SDCAS/ SADS/SRE J25 O/Z IPU EMIF asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable • For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between SADS and SRE: If RENEN = 0, then the SADS/SRE signal functions as the SADS signal. If RENEN = 1, then the SADS/SRE signal functions as the SRE signal. AOE/ SDRAS/ SOE J24 O/Z IPU EMIF asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable AWE/ SDWE/ SWE K26 O/Z IPU EMIF asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable SDCKE L25 O/Z IPU EMIF SDRAM clock-enable (used for self-refresh mode). • If SDRAM is not in system, SDCKE can be used as a general-purpose output. SOE3 R22 O/Z IPU EMIF synchronous memory output-enable for CE3 (for glueless FIFO interface) ARDY L22 I IPU Asynchronous memory ready input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used, unless otherwise noted.) § To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. |
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