TMP32C6411ZLZ datasheet(91/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

RESET TIMING

timing requirements for reset† (see Figure 37)

NO.

−300

UNIT

NO.

MIN

MAX

UNIT

tw(RST)

Width of the RESET pulse (PLL stable)‡

10P

tw(RST)

Width of the RESET pulse (PLL needs to sync up)§

250

µs

tsu(boot)

Setup time, boot configuration bits valid before RESET high¶

4E or 4C#

th(boot)

Hold time, boot configuration bits valid after RESET high¶

tsu(PCLK-RSTH) Setup time, PCLK active before RESET high||

32N

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6 when CLKIN and PLL are stable.

§ This parameter applies to CLKMODE x6 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL

circuit. The PLL, however, may need up to 250

µs to stabilize following device power up or after PLL configuration has been changed. During

that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.

¶ LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 are the boot configuration pins during device reset.

# E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns. Select whichever value is larger for the MIN parameter.

|| N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter must be met.

switching characteristics over recommended operating conditions during reset†kh (see Figure 37)

NO.

PARAMETER

−300

UNIT

NO.

PARAMETER

MIN

MAX

UNIT

td(RSTL-ECKI)

Delay time, RESET low to ECLKIN synchronized internally

3P + 20E

td(RSTH-ECKI)

Delay time, RESET high to ECLKIN synchronized internally

8P + 20E

td(RSTL-ECKO1HZ)

Delay time, RESET low to ECLKOUT1 high impedance

td(RSTH-ECKO1V)

Delay time, RESET high to ECLKOUT1 valid

8P + 20E

td(RSTL-EMIFZHZ)

Delay time, RESET low to EMIF Z high impedance

3P + 4E

td(RSTH-EMIFZV)

Delay time, RESET high to EMIF Z valid

16E

8P + 20E

td(RSTL-EMIFHIV)

Delay time, RESET low to EMIF high group invalid

td(RSTH-EMIFHV)

Delay time, RESET high to EMIF high group valid

8P + 20E

td(RSTL-EMIFLIV)

Delay time, RESET low to EMIF low group invalid

td(RSTH-EMIFLV)

Delay time, RESET high to EMIF low group valid

8P + 20E

td(RSTL-LOWIV)

Delay time, RESET low to low group invalid

td(RSTH-LOWV)

Delay time, RESET high to low group valid

11P

td(RSTL-ZHZ)

Delay time, RESET low to Z group high impedance

td(RSTH-ZV)

Delay time, RESET high to Z group valid

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

kE = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.

hEMIF Z group consists of:

EA[22:3], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE,

SOE3, SDCKE, and PDT.

EMIF high group consists of: HOLDA (when the corresponding HOLD input is high)

EMIF low group consists of:

BUSREQ; HOLDA (when the corresponding HOLD input is low)

Low group consists of:

XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled

(with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details

on the PCI configuration pins, see the Device Configurations section of this data sheet.

Z group consists of:

HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1,

FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0,

GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR,

HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME.

TMP32C6411ZLZ Datasheet(PDF) 91 Page - Texas Instruments

TMP32C6411ZLZ Datasheet(HTML) 91 Page - Texas Instruments

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