TMP32C6411ZLZ datasheet(38/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

SIGNAL

TYPE†

IPD/

‡

DESCRIPTION

NAME

NO.

TYPE†

IPD/

IPU‡

DESCRIPTION

DEVICE CONFIGURATION

LEND

E16

I/O/Z

IPU

Device Endian mode

LEND:

–

Big Endian

− Little Endian (default mode)

HD5/AD5§

I/O/Z

Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-k

Ω resistor

pullup/pulldown resistor on the HD5 pin:

HD5 pin = 0: HPI operates as an HPI16.

(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are

reserved pins in the high-impedance state.)

HD5 pin = 1: HPI operates as an HPI32.

(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)

PCI_EN

AA4

IPD

PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or

PCI peripherals. For more details, see the Device Configurations section of this data sheet.

EEAI

B17

I/O/Z

IPD

PCI EEPROM Auto-Initialization (EEAI) via external EEPROM

If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.

EEAI: 0

− PCI auto-initialization through EEPROM is disabled (default).

− PCI auto-initialization through EEPROM is enabled.

BOOTMODE1

D18

I/O/Z

IPU

Boot mode. Default is reserved. External pullup and/or pulldown resistors must be used to

select a valid bootmode configuration.

BOOTMODE[1:0]: 00 –

No boot

BOOTMODE0

C18

I/O/Z

IPD

BOOTMODE[1:0]: 00 –

No boot

01 − HPI boot

10 − Reserved

11 − EMIF 8-bit ROM boot with default timings (default mode)

ECLKIN_SEL1

B18

I/O/Z

IPD

EMIF clock mode select

ECLKIN_SEL[1:0]: 00 –

ECLKIN (default mode)

ECLKIN_SEL0

A18

I/O/Z

IPD

ECLKIN_SEL[1:0]: 00 –

ECLKIN (default mode)

01 − CPU/4 Clock Rate

10 − CPU/6 Clock Rate

11 − Reserved

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

RESET

AC7

Device reset

NMI

IPD

Nonmaskable interrupt, edge-driven (rising edge)

GP7/EXT_INT7

AF4

General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The

default after reset setting is GPIO enabled as input-only.

GP6/EXT_INT6

AD5

I/O/Z

IPU

General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The

default after reset setting is GPIO enabled as input-only.

When these pins function as External Interrupts [by selecting the corresponding interrupt

GP5/EXT_INT5

AE5

I/O/Z

IPU

• When these pins function as External Interrupts [by selecting the corresponding interrupt

enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently

GP4/EXT_INT4

AF5

enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently

selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).

GP15/PRST§

General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.

GP14/PCLK§

GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.

GP13/PINTA§

GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.

GP12/PGNT§

I/O/Z

GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.

GP11/PREQ§

I/O/Z

GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.

GP10/PCBE3§

GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.

GP9/PIDSEL§

GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.

GP3

AC6

IPD

GPIO 3 pin (I/O/Z).

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-k

Ω resistor should be used, unless otherwise noted.)

§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

TMP32C6411ZLZ Datasheet(PDF) 38 Page - Texas Instruments

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