TMP32C6411ZLZ datasheet(33/119 Pages) TI

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TMS320C6411

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS196H − MARCH 2002 − REVISED JULY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

DEVICE CONFIGURATIONS (CONTINUED)

Table 20. PCI_EN Peripheral Selection (HPI/GP[15:9] or PCI)

PCI_EN Pin

†

PERIPHERALS SELECTED

PCI_EN Pin

[AA4]†

HPI

GP[15:9]

PCI

DESCRIPTION

√

[default] HPI is enabled, GP[15:9] pins can be programmed as GPIO, PCI is

disabled.

This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI

pins (PCBE0, XSP_DO, XSP_DI, XSP_CLK, and XSP_CS) are tied-off (Hi-Z).

Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper

software configuration of the GPIO enable (GPxEN) and direction (GPxDIR)

registers (for more details, see Table 22).

√

PCI is enabled, HPI/GP[15:9] are disabled.

This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed

GPIO/PCI pins function as PCI pins (for more details, see Table 22).

Auto-initialization through PCI EEPROM or initialization via specified PCI default

values is controlled by the EEAI pin, see Table 21.

† The PCI_EN pin is latched at reset and must be driven valid at all times and the user must not switch values throughout device operation.

other device configurations

Table 21 describes the C6411 device configuration pins, which are set up via external pullup/pulldown resistors

through the specified pins. For more details on these device configuration pins, see the Terminal Functions table

and the Debugging Considerations section.

TMP32C6411ZLZ Datasheet(PDF) 33 Page - Texas Instruments