AD9910SLASHPCBZ datasheet(26/60 Pages) AD

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AD9910

Rev. 0 | Page 26 of 60

PFD

PLL_LOOP_FILTER

VCO

÷N

PLL OUT

PLL IN

AVDD

REFCLK PLL

Figure 35. REFCLK PLL External Loop Filter

In the prevailing literature, this configuration yields a third-

order, Type II PLL. To calculate the loop filter component

values, begin with the feedback divider value (N), the gain of

the phase detector (KD), and the gain of the VCO (KV) based on

the programmed VCO SEL bit settings (see Table 1 for KV). The

loop filter component values depend on the desired open-loop

bandwidth (fOL) and phase margin (φ), as follows:

()⎟

⎟

⎠

⎞

⎜⎜

⎝

⎛

sin

(4)

( )

()2

tan

C1 =

(5)

()

( )

() ⎟

⎟

⎠

⎞

⎜⎜

⎝

⎛ −

cos

sin

(6)

where:

KD is equal to the programmed value of ICP.

KV is taken from Table 1.

Ensure that proper units are used for the variables in Equation 4

through Equation 6. ICP must be in amps, not μA as appears in

Table 9; KV must be in Hz/V, not MHz/V as listed in Table 1; the

loop bandwidth (fOL) must be in Hz; the phase margin (φ) must

be in radians.

For example, suppose the PLL is programmed such that

ICP = 287 μA, KV = 625 MHz/V, and N = 25. If the desired loop

bandwidth and phase margin are 50 kHz and 45°, respectively,

then the loop filter component values are R1 = 52.85 Ω, C1 =

145.4 nF, and C2 = 30.11 nF.

PLL LOCK INDICATION

When the PLL is in use, the PLL_LOCK pin provides an active

high indication that the PLL has locked to the REFCLK input

signal. When the PLL is bypassed the PLL_LOCK pin defaults

to Logic 0.

OUTPUT SHIFT KEYING (OSK)

The OSK function (Figure 36) allows the user to control the

output signal amplitude of the DDS. Both a manual and an

automatic mode are available under program control. The

amplitude data generated by the OSK block has priority over

any other functional block that is programmed to deliver

amplitude data to the DDS. Hence, the OSK data source, when

enabled, overrides all other amplitude data sources.

OSK ENABLE

AMPLITUDE SCALE FACTOR

(ASF<15:2>)

AMPLITUDE RAMP RATE

(ASF<31:16>)

AMPLITUDE STEP SIZE

(ASF<1:0>)

MANUAL OSK EXTERNAL

AUTO OSK ENABLE

OSK

DDS CLOCK

TO DDS

AMPLITUDE

CONTROL

PARAMETER

LOAD ARR AT I/O_UPDATE

OSK

CONTROLLER

Figure 36. OSK Block Diagram

The operation of the OSK function is governed by four control

ASF register. The primary control for the OSK block is the OSK

enable bit. When the OSK function is disabled, the OSK input

controls are ignored and the internal clocks shut down.

When the OSK function is enabled, automatic and manual

operation is selected using the select auto OSK bit.

Manual OSK

In manual mode, output amplitude is varied by successive write

operations to the amplitude scale factor portion of the ASF

the output signal is limited by the speed of the serial I/O port.

In manual mode, the OSK pin functionality depends on the

state of the manual OSK external bit. When the OSK pin is

Logic 0, the output amplitude is forced to zero; otherwise, the

output amplitude is set by the amplitude scale factor value.

Automatic OSK

In automatic mode, the OSK function automatically generates a

linear amplitude vs. time profile (or amplitude ramp). The

amplitude ramp is controlled via three parameters: the maximum

amplitude scale factor, the amplitude step size, and the time interval

between steps. The amplitude ramp parameters reside in the 32-bit

ASF register and are programmed via the serial I/O port. The time

interval between amplitude steps is set via the 16-bit amplitude

ramp rate portion of the ASF register (Bits<31:16>). The maximum

amplitude scale factor is set via the 14-bit amplitude scale factor in

the ASF register (Bits<15:2>). The amplitude step size is set via the

2-bit amplitude step size portion of the ASF register (Bits<1:0>).

Additionally, the direction of the ramp (positive or negative slope)

is controlled by the external OSK pin.

AD9910/PCBZ Datasheet(PDF) 26 Page - Analog Devices

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