AD9910SLASHPCBZ datasheet(19/60 Pages) AD

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AD9910

Rev. 0 | Page 19 of 60

PARALLEL DATA PORT MODULATION MODE

In parallel data port modulation mode (Figure 25), the

modulated DDS signal control parameter(s) are supplied

directly from the 18-bit parallel data port.

The data port is partitioned into two sections. The 16 MSBs

make up a 16-bit data-word (D<15:0> pins) and the 2 LSBs

make up a 2-bit destination word (F<1:0> pins). The destination

word defines how the 16-bit data-word is applied to the DDS

signal control parameters. Table 4 defines the relationship

between the destination bits, the partitioning of the 16-bit

data-word, and the destination of the data (in terms of the

DDS signal control parameters). Formatting of the 16-bit

data-word is unsigned binary, regardless of the destination.

When the destination bits indicate that the data-word is

destined as a DDS frequency parameter, the 16-bit data-word

serves as an offset to the 32-bit frequency tuning word in the

FTW register. This means that the 16-bit data-word must

somehow be properly aligned with the 32-bit frequency

parameter. This is accomplished by means of the 4-bit FM gain

word in the programming registers. The FM gain word allows

the user to apply a weighting factor to the 16-bit data-word. In

the default state (0), the 16-bit data-word and the 32-bit word in

the FTW register are LSB aligned. Each increment in the value

of the FM gain word shifts the 16-bit data-word to the left

relative to the 32-bit word in the FTW register, increasing the

influence of the 16-bit data-word on the frequency defined by

the FTW register by a factor of two. The FM gain word effectively

controls the frequency range spanned by the data-word.

Parallel Data Clock (PDCLK)

The AD9910 generates a clock signal on the PDCLK pin that

runs at ¼ of the DAC sample rate (the sample rate of the par-

allel data port). PDCLK serves as a data clock for the parallel

port. By default, each rising edge of PDCLK is used to latch the

18 bits of user-supplied data into the data port. The edge polarity

can be changed through the PDCLK invert bit. Furthermore,

the PDCLK output signal can be switched off using the PDCLK

enable bit. However, even though the output signal is switched

off, it continues to operate internally using the internal PDCLK

timing to capture the data at the parallel port. Note that PDCLK

is Logic 0 when disabled.

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE

I/O_UPDATE

RAM

POWER

DOWN

CONTROL

DAC_RSET

IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMING AND

CONTROL

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt+θ)

Asin (ωt+θ)

DDS

AUX

DAC

8-BIT

DAC

14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

Figure 25. Parallel Data Port Modulation Mode

AD9910/PCBZ Datasheet(PDF) 19 Page - Analog Devices

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