AD9910SLASHPCBZ datasheet(22/60 Pages) AD

22 / 60 page

AD9910

Rev. 0 | Page 22 of 60

FUNCTIONAL BLOCK DETAIL

DDS CORE

The direct digital synthesizer (DDS) block generates a reference

signal (sine or cosine based on the selected DDS sine output

bit). The parameters of the reference signal (frequency, phase,

and amplitude) are applied to the DDS at its frequency, phase

offset, and amplitude control inputs, as shown in Figure 27.

DDS_CLK

FREQUENCY

CONTROL

ANGLE

AMPLITUDE

CONVERSION

(SINE OR

COSINE)

PHASE

OFFSET

CONTROL

TO DAC

(MSBs)

ACCUMULATOR

RESET

MSB ALIGNED

AMPLITUDE

CONTROL

DDS SIGNAL CONTROL PARAMETERS

32-BIT

ACCUMULATOR

Figure 27. DDS Block Diagram

The output frequency (fOUT) of the AD9910 is controlled by the

frequency tuning word (FTW) at the frequency control input to

the DDS. The relationship between fOUT, FTW, and fSYSCLK is

given by

SYSCLK

OUT

FTW

⎟

⎠

⎞

⎜

⎝

⎛

(1)

where FTW is a 32-bit integer ranging in value from 0 to

2,147,483,647 (231 − 1), which represents the lower half of the

full 32-bit range. This range constitutes frequencies from dc to

Nyquist (that is, ½ fSYSCLK).

The FTW required to generate a desired value of fOUT is found

by solving Equation 1 for FTW as given in Equation 2

⎟

⎠

⎞

⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

SYSCLK

OUT

round

FTW

(2)

where the round(x) function rounds the argument (the value of

x) to the nearest integer. This is required because the FTW is

constrained to be an integer value. For example, for fOUT =

41 MHz and fSYSCLK = 122.88 MHz, then FTW = 1,433,053,867

(0x556AAAAB).

Programming an FTW greater than 231 produces an aliased

image that appears at a frequency given by

SYSCLK

OUT

FTW

⎟

⎠

⎞

⎜

⎝

⎛ −

(for FTW ≥ 231)

The relative phase of the DDS signal can be digitally controlled

by means of a 16-bit phase offset word (POW). The phase offset

is applied prior to the angle-to-amplitude conversion block

internal to the DDS core. The relative phase offset (Δθ) is given by

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

360

POW

where the upper quantity is for the phase offset expressed as

radian units and the lower quantity as degrees. To find the

POW value necessary to develop an arbitrary Δθ, solve the

above equation for POW and round the result (in a manner

similar to that described for finding an arbitrary FTW in the

previous paragraphs).

The relative amplitude of the DDS signal can be digitally scaled

(relative to full scale) by means of a 14-bit amplitude scale

factor (ASF). The amplitude scale value is applied at the output

of the angle-to-amplitude conversion block internal to the DDS

core. The amplitude scale is given by

⎟

⎠

⎞

⎜

⎝

⎛

log

ASF

Scale

Amplitude

(3)

where the upper quantity is amplitude expressed as a fraction of

full scale and the lower quantity is expressed in decibels relative

to full scale. To find the ASF value necessary for a particular

scale factor, solve Equation 3 for ASF and round the result (in a

manner similar to that described for finding an arbitrary FTW

in the previous paragraphs).

When the AD9910 is programmed to modulate any of the DDS

signal control parameters, the maximum modulation sample

rate is ¼ fSYSCLK. This means that the modulation signal exhibits

images about multiples of ¼ fSYSCLK. The impact of these images

must be considered when using the device as a modulator.

14-BIT DAC OUTPUT

The AD9910 incorporates an integrated 14-bit, current output

DAC. The output current is delivered as a balanced signal using

two outputs. The use of balanced outputs reduces the potential

amount of common-mode noise present at the DAC output,

offering the advantage of an increased signal-to-noise ratio. An

external resistor (RSET) connected between the DAC_RSET pin

and AGND establishes the reference current. The full-scale

output current of the DAC (IOUT) is produced as a scaled version

of the reference current (see the Auxiliary DAC section). The

recommended value of RSET is 10 kΩ.

Attention should be paid to the load termination to keep the output

voltage within the specified compliance range; voltages developed

beyond this range cause excessive distortion and can damage the

DAC output circuitry.

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