AD9910SLASHPCBZ datasheet(20/60 Pages) AD

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AD9910

Rev. 0 | Page 20 of 60

Table 4. Parallel Port Destination Bits

F<1:0>

D<15:0>

Parameter(s)

Comments

D<15:2>

14-bit amplitude

parameter (unsigned

integer)

Amplitude scales from 0 to 1 − 2−14. D<1:0> are not used.

D<15:0>

16-bit phase parameter

(unsigned integer)

Phase offset ranges from 0 to 2

π(1 − 2−16) radians.

D<15:0>

32-bit frequency

parameter (unsigned

integer)

The alignment of the 16-bit data-word with the 32-bit frequency parameter is controlled

by a 4-bit FM gain word in the programming registers.

D<15:8>

8-bit amplitude

(unsigned integer)

The MSB of the data-word amplitude aligns with the MSB of the DDS 14-bit amplitude

parameter. The 6 LSBs of the DDS amplitude parameter are assigned from Bits<5:0> of the

ASF register. The resulting 14-bit word scales the amplitude from 0 to 1 − 2−14.

D<7:0>

8-bit phase (unsigned

integer)

The MSB of the data-word phase aligns with the MSB of the 16-bit phase parameter of

the DDS. The 8 LSBs of the DDS phase parameter are assigned from Bits<7:0> of the POW

π(1 − 2−16) radians.

Transmit Enable (TxENABLE)

The AD9910 also accepts a user generated signal applied to the

TxENABLE pin that acts as a gate for the user supplied data. By

default, TxENABLE is considered true for Logic 1 and false for

Logic 0. However, the logical behavior of this pin can be reversed

using the TxENABLE invert bit. When TxENABLE is true, the

device latches data into the device on the expected edge of PDCLK

(based on the PDCLK invert bit). When TxENABLE is false,

even though the PDCLK may continue to operate, the device

ignores the data supplied to the port. Furthermore, when the

TxENABLE pin is held false, then the device internally clears

the 18-bit data-words, or it retains the last value present on the

data port prior to TxENABLE switching to the false state (based

on the setting of the data assembler hold last value bit).

Alternatively, instead of operating the TxENABLE pin as a gate,

it can be driven with a clock signal operating at the parallel port

data rate. When driven by a clock signal, the transition from the

false to true state must meet the required setup and hold time

on each cycle to ensure proper operation. The TxENABLE and

PDCLK timing is shown in Figure 26.

FALSE

TRUE

TxENABLE

(BURST)

TxENABLE

(CLOCK)

WORD1

WORD2 WORD3 WORD4 WORDN–4 WORDN

PDCLK

PARALLEL

DATA PORT

tDS

tDH

Figure 26. PDCLK and TxENABLE Timing Diagram

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