AD9910SLASHPCBZ datasheet(47/60 Pages) AD

47 / 60 page

AD9910

Rev. 0 | Page 47 of 60

communication cycle can begin, starting with the instruction

byte write.

I/O_UPDATE—Input/Output Update

The I/O_UPDATE initiates the transfer of written data from

the I/O port buffer to active registers. I/O_UPDATE is active

on the rising edge and its pulse width must be greater than one

SYNC_CLK period. It is either an input or output pin depending

on the programming of the Internal I/O update active bit.

SERIAL I/O TIMING DIAGRAMS

The diagrams below provide basic examples of the timing

relationships between the various control signals of the serial

I/O port. Most of the bits in the register map are not transferred

to their internal destinations until assertion of an I/O update,

which is not included in the timing diagrams that follow.

MSB/LSB TRANSFERS

The AD9910 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by Bit 0 in Control Function

high, the serial port is configured for LSB-first format. If LSB

first is active, all data, including the instruction byte, must

follow LSB-first convention. Note that the highest number

found in the bit range column for each register (see the Register

Map and Bit Descriptions section and Table 16) is the MSB and

the lowest number is the LSB for that register.

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 54. Serial Port Write Timing, Clock Stall Low

DO7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DON'T CARE

SDIO

SCLK

SDO

DO6 DO5 DO4 DO3 DO2 DO1

DO0

Figure 55. 3-Wire Serial Port Read Timing, Clock Stall Low

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 56. Serial Port Write Timing, Clock Stall High

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 57. 2-Wire Serial Port Read Timing, Clock Stall High

AD9910/PCBZ Datasheet(PDF) 47 Page - Analog Devices

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