AD9910SLASHPCBZ datasheet(55/60 Pages) AD

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AD9910

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Control Function Register 2 (CFR2)

Address 0x01; 4 bytes are assigned to this register.

Table 18. Bit Descriptions for CFR2

Bit(s)

Descriptor

Explanation

31:26

Not Available

DROVER Pin Active

Ineffective unless Bit 19 = 1. Refer to DROVER Pin section for details.

Ineffective if Bit 19 = 1 or CFR1<31> = 1 or CFR1<9> = 1.

0 = the amplitude scaler is bypassed and shut down for power conservation (default).

Enable Amplitude Scale

from Single Tone Profiles

1 = the amplitude is scaled by the ASF from the active profile.

This bit is effective without the need for an I/O update.

0 = serial I/O programming is synchronized with the external assertion of the

I/O_UPDATE pin, which is configured as an input pin (default).

Internal I/O Update Active

1 = serial I/O programming is synchronized with an internally generated I/O update

signal (the internally generated signal appears at the I/O_UPDATE pin, which is

configured as an output pin).

SYNC_CLK Enable

0 = The SYNC_CLK pin is disabled; static Logic 0 output.

1 = the SYNC_CLK pin generates a clock signal at ¼ fSYSCLK; used for synchronization of the

serial I/O port (default).

21:20

Digital Ramp Destination

See Table 11 for details. Default is 002. See Digital Ramp Generator (DRG) section for details.

Digital Ramp Enable

0 = disables digital ramp generator functionality (default).

1 = enables digital ramp generator functionality.

See Digital Ramp Generator (DRG) section for details.

0 = disables no-dwell high functionality (default).

Digital Ramp No-Dwell High

1 = enables no-dwell high functionality.

Digital Ramp No-Dwell Low

See Digital Ramp Generator (DRG) section for details.

0 = disables no-dwell low functionality (default).

1 = enables no-dwell low functionality.

Read Effective FTW

0 = a serial I/O port read operation of the FTW register reports the contents of the FTW

1 = a serial I/O port read operation of the FTW register reports the actual 32-bit word

appearing at the input to the DDS phase accumulator.

15:14

I/O Update Rate Control

Ineffective unless Bit 23 = 1. Sets the prescale ratio of the divider that clocks the auto I/O

update timer as follows:

00 = divide-by-1 (default).

01 = divide-by-2.

10 = divide-by-4.

11 = divide-by-8.

13:12

Not Available

PDCLK Enable

0 = the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal

continues to operate and provide timing to the data assembler.

1 = the internal PDCLK signal appears at the PDCLK pin (default).

PDCLK Invert

0 = normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).

1 = inverted PDCLK polarity.

TxEnable Invert

0 = no inversion.

1 = inversion.

Not Available

0 = simultaneous application of amplitude, phase, and frequency changes to the DDS

arrive at the output in the order listed (default).

Matched Latency Enable

1 = simultaneous application of amplitude, phase, and frequency changes to the DDS

arrive at the output simultaneously.

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