AD9910SLASHPCBZ datasheet(24/60 Pages) AD

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AD9910

Rev. 0 | Page 24 of 60

REF_CLK

PLL

VCO

SELECT

DIVIDE

CHARGE

PUMP

OUT

PLL_LOOP_FILTER

ENABLE

PLL_LOOP_FILTER

DRV0

CFR3

<31:30>

REFCLK_OUT

XTAL_SEL

REFCLK

INPUT

SELECT

LOGIC

SYSCLK

ICP

CFR3

<21:19>

CFR3

<7:1>

VCO

CFR3

<26:24>

÷2

INPUT DIVIDER BYPASS

CFR3<15>

PLL ENABLE

CFR3

<8>

INPUT DIVIDER

RESETB

CFR3<14>

Figure 30. REF_CLK Block Diagram

The PLL enable bit is used to choose between the PLL path or

the direct input path. When the direct input path is selected, the

REF_CLK pins must be driven by an external signal source

(single-ended or differential). Input frequencies up to 2 GHz are

supported. For input frequencies greater than 1 GHz, the input

divider must be enabled for proper operation of the device.

When the PLL is enabled, a buffered clock signal is available at

the REFCLK_OUT pin. This clock signal is the same frequency

as the REF_CLK input. This is especially useful when a crystal

is connected, because it gives the user a replica of the crystal

clock for driving other external devices. The REFCLK_OUT

buffer is controlled by two bits as listed in Table 7.

Table 7. REFCLK_OUT Buffer Control

CFR3<31:30>

REFCLK_OUT Buffer

Disabled (tristate)

Low output current

Medium output current

High output current

Crystal Driven REF_CLK

When using a crystal at the REF_CLK input, the resonant

frequency should be approximately 25 MHz. Figure 31 shows

the recommended circuit configuration.

REF_CLK

39pF

XTAL

Figure 31. Crystal Connection Diagram

Direct Driven REF_CLK

When driving the REF_CLK inputs directly from a signal

source either single-ended or differential signals can be used.

With a differential signal source, the REF_CLK pins are driven

with complementary signals and ac-coupled with 0.1 μF

capacitors. With a single-ended signal source, either a single-

ended to differential conversion can be employed or the

REF_CLK input can be driven single-ended directly. In either

case, 0.1 μF capacitors are used to ac couple both REF_CLK

pins to avoid disturbing the internal dc bias voltage of ~1.35 V.

See Figure 32 for more details.

The REF_CLK input resistance is ~2.5 kΩ differential (~1.2 kΩ

single-ended). Most signal sources have relatively low output

impedances. The REF_CLK input resistance is relatively high,

therefore, its effect on the termination impedance is negligible

and can usually be chosen to be the same as the output

impedance of the signal source. The bottom two examples in

Figure 32 assume a signal source with a 50 Ω output impedance.

TERMINATION

REF_CLK

DIFFERENTIAL SOURCE,

DIFFERENTIAL INPUT.

SINGLE-ENDED SOURCE,

DIFFERENTIAL INPUT.

SINGLE-ENDED SOURCE,

SINGLE-ENDED INPUT.

0.1µF

PECL,

LVPECL,

LVDS

DRIVER

REF_CLK

50Ω

0.1µF

BALUN

(1:1)

REF_CLK

0.1µF

50Ω

Figure 32. Direct Connection Diagram

Phase-Locked Loop (PLL) Multiplier

An internal phase-locked loop (PLL) provides users of the

AD9910 the option to use a reference clock frequency that is

significantly lower than the system clock frequency. The PLL

supports a wide range of programmable frequency multiplica-

tion factors (12× to 127×) as well as a programmable charge

pump current and external loop filter components (connected

via the PLL_LOOP_FILTER pin). These features add an extra

layer of flexibility to the PLL, allowing optimization of phase

noise performance and flexibility in frequency plan develop-

ment. The PLL is also equipped with a PLL_LOCK pin.

The PLL output frequency range (fSYSCLK) is constrained to the

range of 420 MHz ≤ fSYSCLK ≤ 1 GHz by the internal VCO. In

addition, the user must program the VCO to one of six operating

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