AD9910SLASHPCBZ datasheet(43/60 Pages) AD

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AD9910

Rev. 0 | Page 43 of 60

SYNCHRONIZATION OF MULTIPLE DEVICES

The internal clocks of the AD9910 provide the timing for the

propagation of data along the baseband signal processing path.

These internal clocks are derived from the internal system clock

(SYSCLK) and are all submultiples of the SYSCLK frequency.

The logic state of all of these clocks in aggregate during any

given SYSCLK cycle defines a unique clock state. The clock state

advances with each cycle of SYSCLK, but the sequence of clock

states is periodic. By definition, multiple devices are synchronized

when their clock states match and they transition between states

simultaneously. Clock synchronization allows the user to asyn-

chronously program multiple devices but synchronously activate

the programming by applying a coincident I/O update to all

devices. It also allows multiple devices to operate in unison when

the parallel port is in use with either the QDUC or interpolating

DAC mode (see Figure 52).

The function of the synchronization logic in the AD9910 is to

force the internal clock generator to a predefined state coincident

with an external synchronization signal applied to the SYNC_IN

pins. If all devices are forced to the same clock state in synchro-

nization with the same external signal, then the devices are, by

definition, synchronized. Figure 49 is a block diagram of the

synchronization function. The synchronization logic is divided

into two independent blocks; a sync generator and a sync receiver,

both of which use the local SYSCLK signal for internal timing.

SYNC

GENERATOR

REF_CLK

SYSCLK

INTERNAL

CLOCKS

SYNC

RECEIVER

SYNC_OUT

REF_CLK

INPUT

CIRCUITRY

SYNC_IN

SYNC_SMP_ERR

SYNC

VALIDATION

DELAY

SYNC STATE

PRESET VALUE

SYNC

TIMING

VALIDATION

DISABLE

SETUP AND

HOLD VALIDATION

SYNC

RECEIVER

ENABLE

SYNC

RECEIVER

DELAY

INPUT DELAY

AND EDGE

DETECTION

Figure 49. Synchronization Circuit Block Diagram

The synchronization mechanism relies on the premise that the

REFCLK signal appearing at each device is edge aligned with all

others as a result of the external REFCLK distribution system

(see Figure 52).

The sync generator block is shown in Figure 50. It is activated

via the sync generator enable bit. It allows for one AD9910 in a

group to function as a master timing source with the remaining

devices slaved to the master.

SYSCLK

SYNC

GENERATOR

ENABLE

SYNC

GENERATOR

DELAY

SYNC

POLARITY

SYNC_OUT

PROGAMMABLE

DELAY

÷16

÷N

LVDS

DRIVER

Figure 50. Sync Generator Diagram

The sync generator produces a clock signal that appears at the

SYNC_OUT pins. This clock is delivered by an LVDS driver

and exhibits a 50% duty cycle. The clock has a fixed frequency

given by

SYSCLK

OUT

SYNC

The clock at the SYNC_OUT pins synchronizes with either the

rising or falling edge of the internal SYSCLK signal as deter-

mined by the sync generator polarity bit. Because the SYNC_OUT

signal is synchronized with the internal SYSCLK of the master

device, the master device SYSCLK serves as the reference timing

source for all slave devices. The user can adjust the output delay

of the SYNC_OUT signal in steps of ~150 ps by programming

the 5-bit sync generator delay word via the serial I/O port. The

programmable output delay facilitates added edge timing

flexibility to the overall synchronization mechanism.

The sync receiver block (shown in Figure 51) is activated via the

sync receiver enable bit. The sync receiver consists of three sub-

sections; the input delay and edge detection block, the internal

clock generator block, and the setup and hold validation block.

The clock generator block remains operational even if the sync

receiver is not enabled.

AD9910/PCBZ Datasheet(PDF) 43 Page - Analog Devices

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