AD9910SLASHPCBZ datasheet(10/60 Pages) AD

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AD9910

Rev. 0 | Page 10 of 60

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

I/O1

Description

1, 20, 72, 86, 87,

93, 97 to 100

Not Connected. Allow device pins to float.

PLL_LOOP_FILTER

PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for

details.

3, 6, 89, 92

AVDD (1.8V)

Analog Core VDD, 1.8 V Analog Supplies.

74 to 77, 83

AVDD (3.3V)

Analog DAC VDD, 3.3 V Analog Supplies.

17, 23, 30, 47,

57, 64

DVDD (1.8V)

Digital Core VDD, 1.8 V Digital Supplies.

11, 15, 21, 28, 45,

56, 66

DVDD_I/O (3.3V)

Digital Input/Output VDD, 3.3 V Digital Supplies.

4, 5, 73, 78, 79,

82, 85, 88, 96

AGND

Analog Ground.

13, 16, 22, 29, 46,

51, 58, 65

DGND

Digital Ground.

SYNC_IN+

Synchronization Signal, Digital Input (Rising Edge Active). The synchronization signal from

the external master to synchronize internal subclocks. See the Synchronization of Multiple

Devices section for details.

SYNC_IN−

Synchronization Signal, Digital Input (Rising Edge Active). The synchronization signal from

the external master to synchronize internal subclocks. See the Synchronization of Multiple

Devices section for details.

SYNC_OUT+

Synchronization Signal, Digital Output (Rising Edge Active). The synchronization signal

from the internal device subclocks to synchronize external slave devices. See the

Synchronization of Multiple Devices section for details.

SYNC_OUT−

Synchronization Signal, Digital Output (Rising Edge Active). The synchronization signal

from the internal device subclocks to synchronize external slave devices. See the

Synchronization of Multiple Devices section for details.

SYNC_SMP_ERR

Synchronization Sample Error, Digital Output (Active High). Sync sample error: a high on

this pin indicates that the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−.

MASTER_RESET

Master Reset, Digital Input (Active High). Master reset: clears all memory elements and sets

registers to default values.

EXT_PWR_DWN

External Power-Down, Digital Input (Active High). A high level on this pin initiates the

currently programmed power-down mode. See the Power-Down Control section of this

document for further details. If unused, connect to ground.

PLL_LOCK

Clock Multiplier PLL Lock, Digital Output (Active High). A high on this pin indicates the

Clock Multiplier PLL has acquired lock to the reference clock input.

RAM_SWP_OVR

RAM Sweep Over, Digital Output (Active High). A high on this pin indicates the RAM sweep

profile has completed.

25 to 27, 31 to 39,

42 to 44, 48

D<15:0>

Parallel Input Bus (Active High).

49, 50

F<1:0>

Modulation Format Pin. Digital input to determine the modulation format.

PDCLK

Parallel Data Clock. This is the digital output (clock). The parallel data clock provides a

timing signal for aligning data at the parallel inputs.

TxENABLE

Transmit Enable. Digital input (active high). In burst mode communications, a high on this

pin indicates new data for transmission. In continuous mode, this pin remains high.

52 to 54

PROFILE<2:0>

Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight

phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the

current contents of all I/O buffers to the corresponding registers. State changes should be

set up on the SYNC_CLK pin.

SYNC_CLK

Output Clock Divided-By-Four. A digital output (clock). Many of the digital inputs on the

chip, such as I/O_UPDATE and PROFILE<2:0> need to be set up on the rising edge of this

signal.

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