AD9910SLASHPCBZ datasheet(23/60 Pages) AD

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AD9910

Rev. 0 | Page 23 of 60

Auxiliary DAC

An 8-bit auxiliary DAC controls the full-scale output current of

the main DAC (IOUT). An 8-bit code word stored in the

appropriate register map location sets IOUT according to the

following equation:

⎟

⎠

⎞

⎜

⎝

⎛ +

CODE

SET

OUT

where RSET is the value of the RSET resistor (in ohms) and CODE

is the 8-bit value supplied to the auxiliary DAC (default is 127).

For example, with RSET = 10,000 and CODE = 127, then IOUT =

20.07 mA.

INVERSE SINC FILTER

The sampled carrier data stream is the input to the digital-to-

analog converter (DAC) integrated onto the AD9910. The

DAC output spectrum is shaped by the characteristic sin(x)/x

(or sinc) envelope, due to the intrinsic zero-order hold effect

associated with DAC generated signals. The sinc enveloped can

be compensated for because its shape is well known. This

envelope restoration function is provided by the inverse sinc

filter preceding the DAC. The inverse sinc filter is implemented as

a digital FIR filter. It has a response characteristic that very

nearly matches the inverse of the sinc envelope. The response of

the inverse sinc filter is shown in Figure 28 (with the sinc

envelope for comparison).

The inverse sinc filter is enabled using a bit in the register map.

The filter tap coefficients are given in Table 6. The filter

operates by predistorting the data prior to its arrival at the DAC

in such a way as to compensate for the sinc envelope that

otherwise distorts the spectrum.

When the inverse sinc filter is enabled, it introduces an ~3.0 dB

insertion loss. The inverse sinc compensation is effective for

output frequencies up to approximately 40% of

the DAC sample rate.

Table 6. Inverse Sinc Filter Tap Coefficients

Tap No.

Tap Value

1, 7

−35

2, 6

+134

3, 5

−562

+6729

In Figure 28, the sinc envelope introduces a frequency

dependent attenuation that can be as much as 4 dB at the

Nyquist frequency (½ of the DAC sample rate). Without the

inverse sinc filter, the DAC output suffers from the frequency

dependent droop of the sinc envelope. The inverse sinc filter

effectively flattens the droop to within ±0.05 dB as shown in

Figure 29, showing the corrected sinc response with the inverse

sinc filter enabled.

–1

–2

–3

–4

0.1

0.2

0.4

0.3

0.5

FREQUENCY RELATIVE TO DAC SAMPLE RATE

INVERSE

SINC

Figure 28. Sinc and Inverse Sinc Responses

–2.8

–2.9

–3.0

–3.1

0.1

0.2

0.4

0.3

0.5

FREQUENCY RELATIVE TO DAC SAMPLE RATE

COMPENSATED RESPONSE

Figure 29. DAC Response with Inverse Sinc Compensation

CLOCK INPUT (REF_CLK)

REF_CLK Overview

The AD9910 supports a number of options for producing the

internal SYSCLK signal (that is, the DAC sample clock) via the

REF_CLK input pins. The REF_CLK input can be driven

directly from a differential or single-ended source, or it can

accept a crystal connected across the two input pins. There is

also an internal phase-locked loop (PLL) multiplier that can be

independently enabled. A block diagram of the REF_CLK

functionality is shown in Figure 30. The various input configu-

rations are controlled by means of the XTAL_SEL pin and

control bits in the CFR3 register. Figure 30 also shows how the

CFR3 control bits are associated with specific functional blocks.

AD9910/PCBZ Datasheet(PDF) 23 Page - Analog Devices

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