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AD9910

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ranges such that fSYSCLK falls within the specified range. Figure 33

and Figure 34 summarize these VCO ranges.

Figure 33 shows the boundaries of the VCO frequency ranges

over the full range of temperature and supply voltage variation

for all devices from the available population. The implication is

that multiple devices chosen at random from the population and

operated under widely varying conditions may require different

values to be programmed into CFR3<26:24> to operate at the

same frequency. For example, Part A chosen randomly from the

population, operating in an ambient temperature of −10°C with

a system clock frequency of 900 MHz may require CFR3<26:24>

to be set to 100b. Whereas Part B chosen randomly from the

population, operating in an ambient temperature of 90°C with a

system clock frequency of 900 MHz may require CFR3<26:24>

to be set to 101b. If a frequency plan is chosen such that the

system clock frequency operates within one set of boundaries

(as shown in Figure 33), the required value in CFR3<26:24> is

consistent from part to part.

Figure 34 shows the boundaries of the VCO frequency ranges

over the full range of temperature and supply voltage variation

for an individual device selected from the population. Figure 34

shows that the VCO frequency ranges for a single device always

overlap when operated over the full range of conditions.

In conclusion, if a user wants to retain a single default value for

CFR3<26:24>, a frequency that falls into one of the ranges

found in Figure 33 should be selected. Additionally, for any

given individual device the VCO frequency ranges overlap,

meaning that any given device exhibits no gaps in its frequency

coverage across VCO ranges over the full range of conditions.

VCO0

VCO1

VCO2

VCO3

VCO4

VCO5

395

495

595

695

795

895

995

FLOW = 400

FHIGH = 460

FLOW = 455

FHIGH = 530

FLOW = 530

FHIGH = 615

FLOW = 760

FHIGH = 875

FLOW = 920

FHIGH = 1030

FLOW = 650

FHIGH = 790

(MHz)

Figure 33. VCO Ranges Including Atypical Wafer Process Skew

335

435

535

635

735

835

935

1035

1135

VCO0

VCO1

VCO2

VCO3

VCO4

VCO5

FLOW = 370

FHIGH = 510

FLOW = 420

FHIGH = 590

FLOW = 500

FHIGH = 700

FLOW = 700

FHIGH = 950

FLOW = 820

FHIGH = 1150

FLOW = 600

FHIGH = 880

(MHz)

Figure 34. Typical VCO Ranges

Table 8. VCO Range Bit Settings

VCO SEL BITS (CFR3<26:24>)

VCO Range

000

VCO0

001

VCO1

010

VCO2

011

VCO3

100

VCO4

101

VCO5

110

PLL Bypassed

111

PLL Bypassed

PLL Charge Pump

The charge pump current (ICP) is programmable to provide the

user with additional flexibility to optimize the PLL performance.

Table 9 lists the bit settings vs. the nominal charge pump

current.

Table 9. PLL Charge Pump Current

ICP (CFR3<21:19>)

Charge Pump Current (ICP in μA)

000

212

001

237

010

262

011

287

100

312

101

337

110

363

111

387

External PLL Loop Filter Components

The PLL_LOOP_FILTER pin provides a connection interface to

attach the external loop filter components. The ability to use

custom loop filter components gives the user more flexibility to

optimize the PLL performance. The PLL and external loop filter

components are shown in Figure 35.

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