AD9910SLASHPCBZ datasheet(34/60 Pages) AD

34 / 60 page

AD9910

Rev. 0 | Page 34 of 60

Note that two-level modulation can be accomplished by using

only one of the three profile pins to toggle between two

different parameter values. Likewise, four-level modulation can

be accomplished by using only two of the three profile pins.

There is no restriction on which profile pins are used.

Ramp Up Timing Diagram

A graphic representation of the ramp up mode appears in

Figure 43, showing both normal and no-dwell operation.

The two upper traces show the progression of the RAM address

from the waveform start address to the waveform end address

for the selected profile. The address value advances by one with

each timeout of the timer internal to the state machine. The

timer period (Δt) is determined by the address ramp rate value

for the selected profile. The two upper traces are differentiated

by the state of the no-dwell high bit.

RAM Direct Switch Mode with Zero-Crossing

The zero-crossing function (enabled with the zero-crossing bit)

is a special feature that is only available in RAM direct switch

mode. The zero-crossing function is only valid if the RAM

playback destination bits specify phase as the DDS signal

control parameter.

WAVEFORM START ADDRESS

WAVEFORM END ADDRESS

M DDS CLOCK CYCLES

WAVEFORM END ADDRESS

NO-DWELL

HIGH = 0

NO-DWELL

HIGH = 1

RAM ADDRESS

RAM_SWP_OVER

I/O_UPDATE

Enabling zero-crossing causes the DDS to delay the application

of a new phase value until such time as the DDS phase

accumulator rolls over from full scale to zero (the point at

which the DDS phase accumulator represents a phase angle that

is at the 360° to 0° transition point). This can be a very

beneficial feature when the DDS is programmed to generate a

sine wave (using the select DDS sine output bit), because the

zero-crossing point of phase for a sine wave corresponds with

the zero-crossing point of amplitude.

In the case of binary phase shift keying (BPSK), the zero-

crossing feature allows the AD9910 to perform the 180° phase

jumps associated with BPSK with only a minimal instantaneous

change in amplitude. This avoids the spectral splatter that

frequently accompanies BPSK modulation.

Although the intent of the zero-crossing feature is for use with

the DDS sine output enabled, it can be used with a cosine

output. In this case, the phase values extracted from RAM are

registered at the DDS when the output amplitude is at its peak

positive value.

Figure 43. Ramp Up Timing Diagram

The circled numbers in Figure 43 indicate specific events

explained as follows:

Event 1—An I/O update or profile change occurs. This event

initializes the state machine to the waveform start address and

sets the RAM_SWP_OVR pin to Logic 0.

RAM Ramp Up Mode

In ramp up mode, upon assertion of an I/O update or a change

of profile, the RAM begins operating as a waveform generator

using the parameters programmed into the selected RAM

profile register. Data is extracted from RAM over the specified

address range and at the specified rate contained in the wave-

form start address, waveform end address, and address ramp

rate values of the selected RAM profile. The data is delivered

to the specified DDS signal control parameter(s) based on the

RAM playback destination bits.

Event 2—The state machine reaches the waveform end address

value for the selected profile. The RAM_SWP_OVR pin

switches to Logic 1. This marks the end of the waveform

generation sequence for normal operation.

Event 3—The state machine switches to the waveform start

address. This marks the end of the waveform generation

sequence for no-dwell operation.

The internal state machine begins extracting data from the

RAM at the waveform start address and continues to extract

data until it reaches the waveform end address. Upon reaching

this address, it either remains at the waveform end address or

returns to the waveform start address as defined by the no-dwell

high bit. Then the state machine halts and the RAM_SWP_OVR

pin goes high.

Changing profiles resets the RAM_SWP_OVR pin to Logic 0,

automatically terminates the current waveform, and initiates the

newly selected waveform.

RAM Ramp Up Internal Profile Control Mode

Ramp up internal profile control mode is invoked via the four

internal profile control bits (rather than through the RAM

profile mode control bits in the RAM profile registers).

AD9910/PCBZ Datasheet(PDF) 34 Page - Analog Devices

AD9910/PCBZ Datasheet(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Descarga

Enlace URL