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AD9910

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Table 14. RAM Internal Profile Control Modes

Internal Profile Control Bits

Waveform Type

Internal Profile

Control Description

0000

Internal profile control disabled.

0001

Burst

Execute Profile 0, then Profile 1, then halt.

0010

Burst

Execute Profile 0 to Profile 2, then halt.

0011

Burst

Execute Profile 0 to Profile 3, then halt.

0100

Burst

Execute Profile 0 to Profile 4, then halt.

0101

Burst

Execute Profile 0 to Profile 5, then halt.

0110

Burst

Execute Profile 0 to Profile 6, then halt.

0111

Burst

Execute Profile 0 to Profile 7, then halt.

1000

Continuous

Execute Profile 0, then 1, continuously.

1001

Continuous

Execute Profile 0 to Profile 2, continuously.

1010

Continuous

Execute Profile 0 to Profile 3, continuously.

1011

Continuous

Execute Profile 0 to Profile 4, continuously.

1100

Continuous

Execute Profile 0 to Profile 5, continuously.

1101

Continuous

Execute Profile 0 to Profile 6, continuously.

1110

Continuous

Execute Profile 0 to Profile 7, continuously.

1111

Invalid.

If any of the internal profile control bits are set, then the RAM

profile mode control bits of the RAM profile registers are

ignored. The no-dwell high bit is ignored in this mode. The

internal profile control mode is identical to ramp up mode,

except that profile switching is done automatically and

internally; the state of the PROFILE<2:0> pins is ignored.

Profiles cycle according to Table 14.

There are two types of waveform generation types available

under internal profile control; burst waveforms and continuous

waveforms. With both types, the state machine begins with the

waveform specified by the waveform start address, waveform

end address, and address ramp rate in Profile 0. After reaching

the waveform end address of Profile 0, the state machine

automatically advances to the next profile and initiates the

specified waveform as defined by the new profile parameters.

After the state machine reaches the waveform end address of

the new profile it advances to the next profile. This action

continues until the state machine reaches the waveform end

address of the last profile as governed by the internal profile

control bits in Register CFR1 per Table 14.

At this point, the next course of action depends on whether the

waveform type is burst or continuous. For burst waveforms, the

state machine halts operation after reaching the waveform end

address of the final profile. For continuous

waveforms, the state machine automatically jumps to Profile 0

and continues the automatic waveform generation by sequentially

advancing through the profiles. This process continues indefi-

nitely until the internal profile control bits are reprogrammed

and an I/O update is asserted.

A burst waveform timing diagram is exemplified in Figure 44.

The diagram assumes that internal profile control bits in

Control Function Register 1 (CFR1) are programmed as 0010,

the start address in RAM Profile 1 is greater than the end address

in RAM Profile 0, and the start address in RAM Profile 2 is

greater than the end address in RAM Profile 1. However,

understand that the block of RAM associated with each profile

can be chosen arbitrarily based on the waveform start address

and waveform end address for each profile. Furthermore, the

example shows how different Δt values associated with each

profile might be utilized.

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