AD9910SLASHPCBZ datasheet(21/60 Pages) AD

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AD9910

Rev. 0 | Page 21 of 60

MODE PRIORITY

The three different modulation modes generate frequency,

phase, and/or amplitude data destined for the DDS signal

control parameters. In addition, the OSK function generates

amplitude data destined for the DDS. Each of these functions is

independently invoked using the appropriate control bit via the

serial I/O port.

The ability to independently activate each of these functions

makes it possible to have multiple data sources attempting to

drive the same DDS signal control parameter. To avoid con-

tention, the AD9910 has a built-in priority system. Table 5

summarizes the priority for each of the DDS signal control

parameters. The rows of the table list data sources for a particular

DDS signal control parameter in descending order of precedence.

For example, if both the RAM and the parallel port are enabled

and both are programmed for frequency as the destination,

then the DDS frequency parameter is driven by the RAM and

not the parallel data port.

Table 5. Data Source Priority

DDS Signal Control Parameters

Frequency

Phase

Amplitude

Priority

Data Source

Conditions

Data Source

Conditions

Data Source

Conditions

Highest

Priority

RAM

RAM enabled and

data destination is

frequency

RAM

RAM enabled and

data destination is

phase or polar

OSK generator

OSK enabled (auto

mode)

DRG

DRG enabled and

data destination is

frequency

DRG

DRG enabled and

data destination is

phase

ASF register

OSK enabled

(manual mode)

Parallel data

port + FTW

Parallel data port

enabled and data

destination is

frequency

Parallel data port

enabled and data

destination is

phase

RAM

RAM enabled and

data destination is

amplitude or polar

FTW register

RAM enabled and

data destination is

phase, amplitude

or polar

Parallel data port

concatenated with

the POW register

LSBs

Parallel data port

enabled and data

destination is polar

DRG

DRG enabled and

data destination is

amplitude

FTW in active

single tone

profile register

DRG enabled and

data destination is

phase or amplitude

POW register

RAM enabled and

destination is

frequency or

amplitude

Parallel data port

enabled and data

destination is

amplitude

FTW in active

single tone

profile register

Parallel data port

enabled and data

destination is

phase, amplitude

or polar

POW in active

single tone profile

DRG enabled and

data destination is

frequency or

amplitude

Parallel data port

concatenated with

the ASF register

LSBs

Parallel data port

enabled and data

destination is

polar

FTW in active

single tone

profile register

None

POW in active

single tone profile

Parallel data port

enabled and data

destination is

frequency or

amplitude

ASF in active single

tone profile

Enable amplitude

scale from Single

Tone Profiles Bit

CFR2<24> set

Lowest

Priority

POW in active

single tone profile

None

No amplitude

scaling

None

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