AD9910SLASHPCBZ datasheet(56/60 Pages) AD

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AD9910

Rev. 0 | Page 56 of 60

Bit(s)

Descriptor

Explanation

Ineffective unless Bit 4 = 1.

Data Assembler Hold Last

Value

0 = the data assembler of the parallel data port internally forces zeros on the data path

and ignores the signals on the D<15:0> and F<1:0> pins while the TxENABLE pin is

Logic 0 (default). This implies that the destination of the data at the parallel data port is

amplitude when TxENABLE is Logic 0.

1 = the data assembler of the parallel data port internally forces the last value received

on the D<15:0> and F<1:0> pins while the TxENABLE pin is Logic 1.

Sync Sample Error Mask

0 = enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization

pulse sampling error.

1 = the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).

See the Parallel Data Port Modulation Mode section for more details.

0 = disables parallel data port modulation functionality (default).

Parallel Data Port Enable

1 = enables parallel data port modulation functionality.

3:0

FM Gain

See the Parallel Data Port Modulation Mode section for more details. Default is 00002.

Control Function Register 3 (CFR3)

Address 0x02; 4 bytes are assigned to this register.

Table 19. Bit Descriptions for CFR3

Bit(s)

Descriptor

Explanation

31:30

DRV0

Controls the REFCLK_OUT pin, (see Table 7 for details); default is 002.

29:27

Not Available

26:24

VCO SEL

Selects frequency band of the REFCLK PLL VCO, (see Table 8 for details); default is 1112.

23:22

Not Available

21:19

ICP

Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 1112.

18:16

Not Available

0 = input divider is selected (default).

REFCLK Input Divider

Bypass

1 = input divider is bypassed.

0 = input divider is reset.

REFCLK Input Divider

ResetB

1 = input divider operates normally (default).

13:9

Not Available

PLL Enable

0 = REFCLK PLL bypassed (default).

1 = REFCLK PLL enabled.

7:1

This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is

00000002.

Not Available

Auxiliary DAC Control Register

Address 0x03; 4 bytes are assigned to this register.

Table 20. Bit Descriptions for DAC Control Register

Bit(s)

Descriptor

Explanation

31:8

Not Available

7:0

FSC

This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary

DAC section); default is 0xFF.

AD9910/PCBZ Datasheet(PDF) 56 Page - Analog Devices

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