Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

AD9910/PCBZ Datasheet(PDF) 48 Page - Analog Devices

No. de pieza AD9910/PCBZ
Descripción Electrónicos  1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
PDF  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9910/PCBZ Datasheet(HTML) 48 Page - Analog Devices

Back Button AD9910/PCBZ Datasheet HTML 44Page - Analog Devices AD9910/PCBZ Datasheet HTML 45Page - Analog Devices AD9910/PCBZ Datasheet HTML 46Page - Analog Devices AD9910/PCBZ Datasheet HTML 47Page - Analog Devices AD9910/PCBZ Datasheet HTML 48Page - Analog Devices AD9910/PCBZ Datasheet HTML 49Page - Analog Devices AD9910/PCBZ Datasheet HTML 50Page - Analog Devices AD9910/PCBZ Datasheet HTML 51Page - Analog Devices AD9910/PCBZ Datasheet HTML 52Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 48 / 60 page
background image
AD9910
Rev. 0 | Page 48 of 60
REGISTER MAP AND BIT DESCRIPTIONS
Table 16. Register Map
Register
Name
(Serial
Address)
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value5
(Hex)
31:24
RAM
Enable
RAM Playback
Destination
Open
0x00
23:16
Manual
OSK
External
Control
Inverse
Sinc Filter
Enable
Open
Internal Profile Control
Select DDS
Sine Output
0x00
15:8
Load LRR
@ I/O
Update
Autoclear
Digital
Ramp
Accum.
Autoclear
Phase
Accum.
Clear
Digital
Ramp
Accum.
Clear
Phase
Accum.
Load ARR
@ I/O
Update
OSK
Enable
Select Auto
OSK
0x00
CFR1—
Control
Function
Register 1
(0x00)
7:0
Digital
Power-
Down
DAC
Power-
Down
REFCLK
Input
Power-
Down
Aux DAC
Power-
Down
External
Power-
Down
Control
Open
SDIO
Input Only
LSB First
0x00
31:24
Open
DROVER
Pin Active
Enable
Amplitude
Scale from
Single Tone
Profiles
0x00
23:16
Internal
I/O
Update
Active
SYNC_CLK
Enable
Digital Ramp
Destination
Digital
Ramp
Enable
Digital
Ramp
No-Dwell
High
Digital
Ramp
No-Dwell
Low
Read
Effective
FTW
0x40
15:8
I/O Update Rate Control
Open
PDCLK
Enable
PDCLK
Invert
TxEnable
Invert
Open
0x08
CFR2—
Control
Function
Register 2
(0x01)
7:0
Matched
Latency
Enable
Data
Assembler
Hold Last
Value
Sync
Sample
Error Mask
Parallel
Data Port
Enable
FM Gain
0x20
31:24
DRV0<1:0>
Open<5:3>
VCO SEL<2:0>
0x1F
23:16
Open
ICP<2:0>
Open
0x3F
15:8
REFCLK
Input
Divider
Bypass
REFCLK
Input
Divider
ResetB
Open
PLL Enable
0x40
CFR3—
Control
Function
Register 3
(0x02)
7:0
N<6:0>
Open
0x00
31:24
Open
0x00
23:16
Open
0x00
15:8
Open
0x7F
Auxiliary
DAC
Control
(0x03)
7:0
FSC<7:0>
0x7F
31:24
I/O Update Rate<31:24>
0xFF
23:16
I/O Update Rate<23:16>
0xFF
15:8
I/O Update Rate<15:8>
0xFF
I/O Update
Rate (0x04)
7:0
I/O Update Rate<7:0>
0xFF
31:24
Frequency Tuning Word<31:24>
0x00
23:16
Frequency Tuning Word<23:16>
0x00
15:8
Frequency Tuning Word<15:8>
0x00
FTW—
Frequency
Tuning
Word
(0x07)
7:0
Frequency Tuning Word<7:0>
0x00



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com