AD9910SLASHPCBZ datasheet(38/60 Pages) AD

38 / 60 page

AD9910

Rev. 0 | Page 38 of 60

WAVEFORM START ADDRESS

WAVEFORM END ADDRESS

PROFILE0

RAM ADRESS

RAM_SWP_OVER

I/O_UPDATE

M DDS CLOCK CYCLES

Figure 46. Bidirectional Ramp Timing Diagram

If the PROFILE0 pin changes states before the state machine

reaches the programmed start or end address, the internal timer

is restarted and the direction of the address counter is reversed.

Figure 46 is a graphic representation of the bidirectional ramp

mode. It shows the action of the state machine in response to

the PROFILE0 pin, and the response of the RAM_SWP_OVR pin.

The RAM_SWP_OVR pin switches to Logic 1 when the state

machine reaches the waveform end address. It remains Logic 1

until the state machine reaches the waveform start address and

the PROFILE0 pin transitions from Logic 0 to Logic 1.

The circled numbers in Figure 46 indicate specific events as

follows:

Event 1—An I/O update or profile change activates the RAM

bidirectional ramp mode. The state machine initializes to the

waveform start address and the RAM_SWP_OVR pin is set to

Logic 0.

Event 2—PROFILE0 pin switches to Logic 1. The state machine

begins incrementing the RAM address counter.

Event 3—PROFILE0 pin remains at Logic 1 long enough for

the state machine to reach the waveform end address. The

RAM_SWP_OVR pin switches to Logic 1 accordingly.

Event 4—PROFILE0 pin switches to Logic 0. The state

machine begins decrementing the RAM address counter.

The RAM_SWP_OVR pin remains at Logic 1.

Event 5—PROFILE0 pin switches to Logic 1. The state machine

resets its internal timer and reverses the direction of the RAM

address counter (that is, it starts to increment). No change of

the RAM_SWP_OVR state because the waveform start address

has not yet been reached.

Event 6—PROFILE0 pin switches to Logic 0. The state machine

resets its internal timer and again reverses the direction of the RAM

address counter. The RAM_SWP_OVR state does not change.

Event 7—PROFILE0 pin remains at Logic 0 long enough for the

state machine to reach the waveform start address. There is no

change in the RAM_SWP_OVR state.

Event 8—PROFILE0 pin switches to Logic 1. The state machine

resets its internal timer and begins incrementing the RAM

address counter. The RAM_SWP_OVR pin switches to Logic 0

because both the waveform start address was reached and the

PROFILE0 pin transitioned from Logic 0 to Logic 1.

RAM Continuous Bidirectional Ramp Mode

In continuous bidirectional ramp mode, upon assertion of an

I/O update or a change of profile, the RAM begins operating as

a waveform generator using the parameters programmed into

the RAM profile designated by the profile pins. Data is extracted

from RAM over the specified address range and at the specified

rate contained in the waveform start address, waveform end

address, and address ramp rate values of the selected RAM

profile. The data is delivered to the specified DDS signal control

parameter(s) based on the RAM playback destination bits. The

no-dwell high bit is ignored in this mode.

With the continuous bidirectional ramp mode activated via an

I/O update or profile change, the internal state machine begins

extracting data from the RAM at the waveform start address

and incrementing the address counter until it reaches the

waveform end address. At this point, the state machine

automatically reverses the direction of the address counter and

begins decrementing through the address range. Whenever one

of the terminal addresses is reached, the state machine reverses

the address counter; the process continues indefinitely.

AD9910/PCBZ Datasheet(PDF) 38 Page - Analog Devices

AD9910/PCBZ Datasheet(HTML) 38 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Descarga

Enlace URL