AD9910SLASHPCBZ datasheet(6/60 Pages) AD

6 / 60 page

AD9910

Rev. 0 | Page 6 of 60

Parameter

Conditions/Comments

Min

Typ

Max

Unit

201.1 MHz Analog Output

±500 kHz

–87

dBc

±125 kHz

–87

dBc

±12.5 kHz

–91

dBc

301.1 MHz Analog Output

±500 kHz

–86

dBc

±125 kHz

–86

dBc

±12.5 kHz

–88

dBc

401.3 MHz Analog Output

±500 kHz

–84

dBc

±125 kHz

–84

dBc

±12.5 kHz

–85

dBc

SERIAL PORT TIMING CHARACTERISTICS

Maximum SCLK Frequency

Mbps

Minimum SCLK Clock Pulse Width

Low

High

Maximum SCLK Rise/Fall Time

Minimum Data Setup Time to SCLK

Minimum Data Hold Time to SCLK

Maximum Data Valid Time in Read Mode

I/O_UPDATE/PS0/PS1/PS2 TIMING

CHARACTERISTICS

Minimum Pulse Width

High

SYNC_CLK cycle

Minimum Setup Time to SYNC_CLK

Minimum Hold Time to SYNC_CLK

Tx_ENABLE and 16-BIT PARALLEL (DATA) BUS

TIMING

Maximum PDCLK Frequency

250

MHz

Tx_ENABLE/Data Setup Time (to PDCLK)

Tx_ENABLE/Data Hold Time (to PDCLK)

MISCELLANEOUS TIMING CHARACTERISTICS

Wake-Up Time2

Fast Recovery

SYSCLK cycles

Full Sleep Mode

150

μs

Minimum Reset Pulse Width High

SYSCLK cycles3

DATA LATENCY (PIPE_LINE DELAY)

Data Latency, Single Tone or using Profiles

Frequency, Phase, Amplitude-to-DAC Output

Matched latency enabled and OSK

enabled

SYSCLK cycles

Frequency, Phase-to-DAC Output

Matched latency enabled and OSK

disabled

SYSCLK cycles

Matched latency disabled

SYSCLK cycles

Amplitude-to-DAC Output

Matched latency disabled

SYSCLK cycles

Data Latency using RAM Mode

Frequency, Phase-to-DAC Output

Matched latency enabled/disabled

SYSCLK cycles

Amplitude-to-DAC Output

Matched latency enabled

106

SYSCLK cycles

Matched latency disabled

SYSCLK cycles

Data Latency, Sweep Mode

Frequency, Phase-to-DAC Output

Matched latency enabled/disabled

SYSCLK cycles

Amplitude-to-DAC Output

Matched latency enabled

SYSCLK cycles

Matched latency disabled

SYSCLK cycles

Data Latency, 16-Bit Input Modulation Mode

Frequency, Phase-to-DAC Output

Matched latency enabled

103

SYSCLK cycles

Matched latency disabled

SYSCLK cycles

AD9910/PCBZ Datasheet(PDF) 6 Page - Analog Devices

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