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AD9910

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WAVEFORM START

ADDRESS 0

WAVEFORM END

ADDRESS 0

WAVEFORM START

ADDRESS 1

WAVEFORM END

ADDRESS 1

RAM_SWP_OVER

RAM PROFILE

RAM

ADDRESS

I/O_UPDATE

10 11

Figure 45. Internal Profile Control Timing Diagram (Continuous)

Internal Profile Control Continuous Waveform

Timing Diagram

An example of an internal profile control, continuous waveform

timing diagram is shown in Figure 45. The diagram assumes

that Internal Profile Control<20:17> is programmed as 1000. It

also assumes that the start address in RAM Profile 1 is greater

than the end address in RAM Profile 0.

The gray bar across the top indicates the time interval over

which the designated profile is in effect. The circled numbers

indicate specific events.

Event 1—An I/O update registers the fact that internal profile

control bits (in Control Function Register 1) are programmed

to 1000. The RAM_SWP_OVR pin is set to Logic 0. The state

machine is initialized to the waveform start address of RAM

Profile 0 and begins incrementing through the address range for

RAM Profile 0 at intervals of Δt0 (as specified by the address

step rate for RAM Profile 0).

Event 2—The state machine reaches the waveform end address

of RAM Profile 0 and the RAM_SWP_OVR pin generates a

positive pulse spanning two DDS clock cycles.

Event 3—Having reached the waveform end address of RAM

Profile 0, the next expiration of the internal timer causes the

state machine to advance to RAM Profile 1. The state machine

is initialized to the waveform start address of RAM Profile 1

and begins incrementing through the address range for RAM

Profile 1 at intervals of Δt1.

Event 4—The state machine reaches the waveform end address

of RAM Profile 1 and the RAM_SWP_OVR pin generates a

positive pulse spanning two DDS clock cycles.

Event 5—Having reached the waveform end address of RAM

Profile 1, the next expiration of the internal timer causes the

state machine to jump back to RAM Profile 0. The state

machine initializes to the waveform start address of RAM

Profile 0 and begins incrementing through the address range for

RAM Profile 0 at intervals of Δt0.

Event 6 and Event 8—Same as Event 2 and Event 4, respectively.

Event 5 to Event 8—Repeat indefinitely until the internal profile

control bits are reprogrammed and an I/O update is asserted.

RAM Bidirectional Ramp Mode

In bidirectional ramp mode, upon assertion of an I/O update,

the RAM begins operating as a waveform generator using the

parameters programmed only into RAM Profile 0 (unlike ramp

up mode, which uses all eight profiles). Data is extracted from

RAM over the specified address range and at the specified rate

contained in the waveform start address, waveform end address,

and address ramp rate values of the selected RAM profile. The

data is delivered to the specified DDS signal control

parameter(s) based on the RAM playback destination bits.

The PROFILE<2:1> pins are ignored by the internal logic in

this mode. When a RAM profile programmed to operate in this

mode is selected, no other RAM profiles can be selected until

the active RAM profile is reprogrammed with a different RAM

operating mode. The no-dwell high bit is ignored in this mode.

With the bidirectional ramp mode activated via an I/O update

or profile change, the internal state machine readies to extract

data from the RAM at the waveform start address. Data

extraction begins when PROFILE0 is Logic 1, which instructs

the state machine to begin incrementing through the address

range. As long as the PROFILE0 pin remains Logic 1, the state

machine continues to extract data until it reaches the waveform

end address. At this point, the state machine halts until the

PROFILE0 pin is Logic 0 instructing the state machine to begin

decrementing through the address range. As long as the

PROFILE0 pin is Logic 0, the state machine continues to extract

data until it reaches the waveform start address. At this point,

the state machine halts until the PROFILE0 pin is Logic 1.

AD9910/PCBZ Datasheet(PDF) 37 Page - Analog Devices

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