AD9910SLASHPCBZ datasheet(53/60 Pages) AD

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AD9910

Rev. 0 | Page 53 of 60

The serial I/O port registers span an address range of 0 to 23

(0x00 to 0x16 in hexadecimal notation). This represents a total

of 24 registers. However, two of these registers are unused

yielding a total of 22 available registers. The unused registers are

The number of bytes assigned to the registers varies from

depth; each contains the number of bytes necessary for its

particular function. Additionally, the registers are assigned

names according to their functionality. In some cases, a register

is given a mnemonic descriptor. For example, the register at

Serial Address 0x00 is named Control Function Register 1 and

is assigned the mnemonic CFR1.

The following section provides a detailed description of each bit

in the AD9910 register map. Of course, for cases in which a

group of bits serve a specific function, the entire group is

considered as a binary word and described in aggregate.

This section is organized in sequential order of the serial

addresses of the registers. Each subheading includes the register

name and optional register mnemonic (in parentheses). Also

given is the serial address in hexadecimal format and the

number of bytes assigned to the register.

Following each subheading is a table containing the individual

bit descriptions for that particular register. The location of the

bit(s) in the register are indicated by a single number or a pair

of numbers separated by a colon. That is, a pair of numbers

(A:B) indicates a range of bits from the most significant (A) to

the least significant (B). For example, 5:2 implies Bit Position 5

down to Bit Position 2, inclusive, with Bit 0 identifying the LSB

of the register.

Unless otherwise stated, programmed bits are not transferred to

their internal destinations until the assertion of the I/O_UPDATE

pin or a profile change.

Control Function Register 1 (CFR1)

Address 0x00; 4 bytes are assigned to this register.

Table 17. Bit Description for CFR1

Bit(s)

Descriptor

Explanation

RAM Enable

0 = disables RAM functionality (default).

1 = enables RAM functionality (required for both load/retrieve and playback operation).

30:29

RAM Playback Destination

See Table 12 for details; default is 002.

28:24

Not Available

Ineffective unless Bits<9:8> = 102.

Manual OSK External

Control

0 = OSK pin inoperative (default).

1 = OSK pin enabled for manual OSK control (see Output Shift Keying (OSK) section for

details).

Inverse Sinc Filter Enable

0 = Inverse sinc filter bypassed (default).

1 = Inverse sinc filter active.

Not Available

20:17

Internal Profile Control

Ineffective unless Bit 31 = 1. These bits are effective without the need for an I/O update.

See Table 14 for details. Default is 00002.

Select DDS Sine Output

0 = cosine output of the DDS is selected (default).

1 = sine output of the DDS is selected.

Load LRR @ I/O Update

Ineffective unless CFR2<19> = 1.

0 = normal operation of the digital ramp timer (default).

1 = digital ramp timer loaded any time I/O_UPDATE is asserted or a profile change occurs.

0 = normal operation of the DRG accumulator (default).

Autoclear Digital Ramp

Accumulator

1 = the ramp accumulator is reset for one cycle of the DDS clock after which the

accumulator automatically resumes normal operation. As long as this bit remains set, the

ramp accumulator is momentarily reset each time an I/O update is asserted or a profile

change occurs. This bit is synchronized with either an I/O update or a profile change and

the next rising edge of SYNC_CLK.

0 = normal operation of the DDS phase accumulator (default).

Autoclear Phase

Accumulator

1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a

profile change occurs.

AD9910/PCBZ Datasheet(PDF) 53 Page - Analog Devices

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