ATtiny44 datasheet(125/236 Pages) ATMEL

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8006H–AVR–10/09

ATtiny24/44/84

14.5.2

USIBR – USI Data Buffer

Instead of reading data from the USI Data Register the USI Buffer Register can be used. This

makes controlling the USI less time critical and gives the CPU more time to handle other pro-

gram tasks. USI flags as set similarly as when reading the USIDR register.

The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has

been completed.

14.5.3

USISR – USI Status Register

The Status Register contains interrupt flags, line status flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has

been detected. When three-wire mode or output disable mode has been selected any edge on

the SCK pin will set the flag.

If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener-

ated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit.

Clearing this bit will release the start detection hold of USCL in two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). If the

USIOIE bit in USICR and the Global Interrupt Enable Flag are set an interrupt will also be gener-

ated when the flag is set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in two-wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When two-wire mode is selected, the USIPF Flag is set (one) when a stop condition has been

detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag.

This signal is useful when implementing two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The

flag is only valid when two-wire mode is used. This signal is useful when implementing Two-wire

bus master arbitration.

• Bits 3:0 – USICNT3:0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

Bit

0x10 (0x30)

MSB

LSB

USIBR

Read/Write

Initial Value

Bit

0x0D (0x2D)

USISIF

USIOIF

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USISR

Read/Write

R/W

RR/W

R/W

Initial Value

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