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ATtiny44 Datasheet(PDF) 67 Page - ATMEL Corporation |
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ATtiny44 Datasheet(HTML) 67 Page - ATMEL Corporation |
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67 / 236 page ![]() 67 8006H–AVR–10/09 ATtiny24/44/84 10.3 Register Description 10.3.1 MCUCR – MCU Control Register • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con- figuring the Pin” on page 55 for more details about this feature. 10.3.2 PORTA – Port A Data Register 10.3.3 DDRA – Port A Data Direction Register Table 10-9. Overriding Signals for Alternate Functions in PB1..PB0 Signal Name PB1/XTAL2/PCINT9 PB0/XTAL1/PCINT8 PUOE EXT_OSC (1) 1. EXT_OSC = crystal oscillator or low frequency crystal oscillator is selected as system clock. EXT_CLOCK (2) + EXT_OSC(1) 2. EXT_CLOCK = external clock is selected as system clock. PUOV 0 0 DDOE EXT_OSC(1) EXT_CLOCK(2) + EXT_OSC(1) DDOV 0 0 PVOE EXT_OSC(1) EXT_CLOCK(2) + EXT_OSC(1) PVOV 0 0 PTOE 0 0 DIEOE EXT_OSC (1)+ PCINT9 • PCIE1 EXT_CLOCK(2) + EXT_OSC(1) + (PCINT8 • PCIE1) DIEOV EXT_OSC(1) • PCINT9 • PCIE1 ( EXT_CLOCK(2) • PWR_DOWN ) + (EXT_CLOCK(2) • EXT_OSC(1) • PCINT8 • PCIE1) DI PCINT9 Input CLOCK/PCINT8 Input AIO XTAL2 XTAL1 Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR Read/Write R/W R/W R/W R/W R/W R/W RR Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 0x1B (0x3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 210 0x1A (0x3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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