ATtiny44 datasheet(66/236 Pages) ATMEL

66 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

• Port B, Bit 3 – RESET/dW/PCINT11

• RESET: External Reset input is active low and enabled by unprogramming (“1”) the

RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when

the pin is used as the RESET pin.

•dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are

unprogrammed, the debugWIRE system within the target device is activated. The RESET

port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled

and becomes the communication gateway between target and emulator.

•PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt

source for pin change interrupt 1.

Table 10-8 on page 66 and Table 10-9 on page 67 relate the alternate functions of Port B to the

overriding signals shown in Figure 10-5 on page 59.

Table 10-8.

Overriding Signals for Alternate Functions in PB3..PB2

Signal

Name

PB3/

RESET/dW/

PCINT11

PB2/INT0/OC0A/CKOUT/PCINT10

PUOE

RSTDISBL (1)+ DEBUGWIRE_ENABLE (2)

RSTDISBL is 1 when the Fuse is “0” (Programmed).

DebugWIRE is enabled wheb DWEN Fuse is programmed and Lock bits are unprogrammed.

CKOUT

PUOV

DDOE

RSTDISBL(1) + DEBUGWIRE_ENABLE(2)

CKOUT

DDOV

DEBUGWIRE_ENABLE(2) • debugWire

Transmit

PVOE

RSTDISBL(1) + DEBUGWIRE_ENABLE(2)

CKOUT + OC0A enable

PVOV

CKOUT • System Clock + CKOUT • OC0A

PTOE

DIEOE

RSTDISBL(1) + DEBUGWIRE_ENABLE(2) +

PCINT11 • PCIE1

PCINT10 • PCIE1 + INT0

DIEOV

DEBUGWIRE_ENABLE(2) + (RSTDISBL(1) •

PCINT11 • PCIE1)

PCINT10 • PCIE1 + INT0

dW/PCINT11 Input

INT0/PCINT10 Input

AIO

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