ATtiny44 datasheet(35/236 Pages) ATMEL

35 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

7.2.1

Limitations

BOD disable functionality has been implemented in the following devices, only:

• ATtiny24, revision E, and newer

• ATtiny44, revision D, and newer

• ATtiny84, revision B, and newer

Revisions are marked on the device package and can be located as follows:

• Bottom side of packages 14P3 and 14S1

• Top side of package 20M1

7.3

Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 37, pro-

vides a method to reduce power consumption by stopping the clock to individual peripherals.

The current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current

of I/O Modules” on page 185 for examples.

7.4

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

7.4.1

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. See “Analog to Digital Converter” on page 132 for

details on ADC operation.

7.4.2

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep

modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is

set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-

abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,

independent of sleep mode. See “Analog Comparator” on page 129 for details on how to config-

ure the Analog Comparator.

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