ATtiny44 datasheet(122/236 Pages) ATMEL

122 / 236 page

122

8006H–AVR–10/09

ATtiny24/44/84

Figure 14-4. Two-wire Mode Operation, Simplified Diagram

The data direction is not given by the physical layer. A protocol, like the one used by the TWI-

bus, must be implemented to control the data flow.

Figure 14-5. Two-wire Mode, Typical Timing Diagram

Referring to the timing diagram (Figure 14-5), a bus transfer involves the following steps:

The start condition is generated by the master by forcing the SDA low line while keep-

ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the

USI Data Register, or by setting the corresponding bit in the PORTA register to zero.

Note that the Data Direction Register bit must be set to one for the output to be

enabled. The start detector logic of the slave device (see Figure 14-6 on page 123)

detects the start condition and sets the USISIF Flag. The flag can generate an interrupt

if necessary.

In addition, the start detector will hold the SCL line low after the master has forced a

negative edge on this line (B). This allows the slave to wake up from sleep or complete

other tasks before setting up the USI Data Register to receive the address. This is done

by clearing the start condition flag and resetting the counter.

MASTER

SLAVE

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Two-wire Clock

Control Unit

HOLD

SCL

PORTxn

SDA

SCL

VCC

ADDRESS

1 - 7

R/W

ACK

1 - 8

DATA

ACK

1 - 8

DATA

SDA

SCL

ATtiny44 Datasheet(PDF) 122 Page - ATMEL Corporation

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