ATtiny44 datasheet(98/236 Pages) ATMEL

98 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or

OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max-

imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =

14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-7 on page 98. The

figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is

in the timing diagram shown as a histogram for illustrating the single-slope operation. The dia-

gram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the

TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt

flag will be set when a compare match occurs.

Figure 12-7. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition

the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or

ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP

value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low

FPWM

TOP

()

log

()

log

-----------------------------------

TCNTn

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

ATtiny44 Datasheet(PDF) 98 Page - ATMEL Corporation

ATtiny44 Datasheet(HTML) 98 Page - ATMEL Corporation

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