ATtiny44 datasheet(126/236 Pages) ATMEL

126 / 236 page

126

8006H–AVR–10/09

ATtiny24/44/84

The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe

bits. The clock source depends on the setting of the USICS1:0 bits.

For external clock operation a special feature is added that allows the clock to be generated by

writing to the USITC strobe bit. This feature is enabled by choosing an external clock source

(USICS1 = 1) and writing a one to the USICLK bit.

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) can still be used by the counter.

14.5.4

USICR – USI Control Register

The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the

clock and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt

and USISIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed

immediately. Refer to the USISIF bit description on page 125 for further details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and

USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme-

diately. Refer to the USIOIF bit description on page 125 for further details.

• Bit 5:4 – USIWM1:0: Wire Mode

These bits set the type of wire mode to be used, as shown in Table 14-1 on page 127.

Basically, only the function of the outputs are affected by these bits. Data and clock inputs are

not affected by the mode selected and will always have the same function. The counter and USI

Data Register can therefore be clocked externally and data input sampled, even when outputs

are disabled.

Bit

654

0x0D (0x2D)

USISIE

USIOIE

USIWM1

USIWM0

USICS1

USICS0

USICLK

USITC

USICR

Read/Write

R/W

R/WW

Initial Value

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